Purpose

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

Design/methodology/approach

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

Findings

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

Originality/value

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

中文翻译：

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4:1 多路复用器，采用低功耗高速多米诺技术，用于使用 FinFET 的大型扇入栅极

目的

本文旨在提出一种新的基于鳍式场效应晶体管 (FinFET) 的多米诺技术低功率串联脚驱动晶体管逻辑，采用 32 nm 技术，并通过瞬态分析检查其性能参数。

设计/方法/方法

在所提出的技术中，通过电流分流来减少页脚节点处的漏电流，以提高电路在平均功耗、传播延迟和噪声容限方面的性能。使用 HSPICE 在 0.9 V 电源电压下，在 FinFET 32 nm 技术的 FinFET 和互补金属氧化物半导体技术中对现有和提议的技术进行模拟，用于 2、4、8 和 16 输入多米诺或门。

发现

与基于电流镜的工艺变化容忍 (CPVT) 技术相比，所提出的技术在 FinFET 短栅极 (SG) 模式下最大功率降低了 77.74%，在低功率 (LP) 模式下最大延迟降低了 51.34%。频率为 100 MHz 的 CPVT 技术。与 FinFET SG 模式下的不同现有技术相比，所提出电路的单位噪声增益高 1.10 至 1.54 倍，而 FinFET LP 模式下则高 1.11 至 1.71 倍。与现有的多米诺技术相比，所提出电路的品质因数高出 15.77 倍。

原创性/价值

该研究提出了一种新的基于 FinFET 的多米诺骨牌技术，并显示了在功率、延迟、面积和噪声性能方面的改进。所提出的设计可用于实现高速数字电路，例如微处理器和存储器。