A new low-capacitance clamp is introduced for high-voltage-tolerant and high-speed interface applications. An embedded stacking architecture is proposed to address latch-up-immune design requirements without degradation in the electrostatic discharge (ESD) stress-handling capability, leakage, or capacitance. Thanks to a parallel current conduction path activated during ESD stress, a state-of-the-art failure threshold current per unit area is obtained for high-voltage-tolerant interface applications in sub-28-nm CMOS process technologies. The device design concept introduced in this article facilitates the implementation of compact, high-performance interface applications, extended in general to protection clamp devices requiring a higher holding voltage.

中文翻译：

---

一种用于高速应用的新型低电容高压耐受保护钳

为耐高压和高速接口应用引入了一种新的低电容钳位。提出了一种嵌入式堆叠架构来解决闩锁免疫设计要求，而不会降低静电放电 (ESD) 应力处理能力、泄漏或电容。由于在 ESD 应力期间激活了并行电流传导路径，因此在亚 28 纳米 CMOS 工艺技术中为耐高压接口应用获得了最先进的每单位面积故障阈值电流。本文中介绍的器件设计概念有助于实现紧凑、高性能的接口应用，通常扩展到需要更高保持电压的保护钳位器件。