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A Compact Model for ISPP of 3-D Charge-Trap NAND Flash Memories
IEEE Transactions on Electron Devices ( IF 2.9 ) Pub Date : 2020-08-01 , DOI: 10.1109/ted.2020.3000448
Minsoo Kim , Sungbak Kim , Hyungcheol Shin

We developed a compact model for program transient simulation of 3-D charge-trap NAND flash on a bitline (BL) string level. By implanting the trapped charge parameters and the solutions obtained from modified 1-D Poisson equation into our unit cell model, we suggest that our model shows better accuracy compared to the existing model. After fitting the measured incremental step pulse programming (ISPP) data with the best accuracy, we investigated our model dependence on parameters relevant to electron tunneling/capture/emission and channel scaling. Also, the simulation results from various pulse conditions are investigated. Finally, program-inhibit characteristics by isolated channel were simulated and analyzed. Thus, we propose a widely available, highly accurate, and physics-based compact model for program operation of 3-D charge-trap NAND flash memories.

中文翻译:

3-D 电荷陷阱 NAND 闪存的 ISPP 紧凑模型

我们开发了一个紧凑模型,用于位线 (BL) 串级 3-D 电荷陷阱 NAND 闪存的程序瞬态仿真。通过将捕获的电荷参数和从修改后的一维泊松方程获得的解决方案植入我们的晶胞模型,我们建议我们的模型与现有模型相比显示出更好的精度。在以最佳精度拟合测量的增量步进脉冲编程 (ISPP) 数据后,我们研究了我们的模型对与电子隧道/捕获/发射和通道缩放相关的参数的依赖性。此外,还研究了各种脉冲条件下的模拟结果。最后,对隔离通道的编程抑制特性进行了仿真和分析。因此,我们提出了一种广泛可用的、高度准确的、
更新日期:2020-08-01
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