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Probability-based Address Translation for Flash SSDs
IEEE Computer Architecture Letters ( IF 2.3 ) Pub Date : 2020-07-01 , DOI: 10.1109/lca.2020.3006529
Junsu Im , Hanbyeol Kim , Yumin Won , Jiho Oh , Minjae Kim , Sungjin Lee

Thanks to the advance of NAND scaling technologies, an ultra-scale SSD (e.g., $>$> 100 TB) is introduced to markets. This rapid increase of SSD capacity, however, comes at the cost of more DRAM which resides in an SSD controller for logical-to-physical (L2P) address translation. Many have proposed various address translation algorithms to reduce DRAM, but they fail to provide short read latency, in particular when a workload has weak locality. This letter proposes a novel probability-based address translation algorithm, called ProbFTL. In contrast to existing translation techniques that maintain exact L2P mapping, ProbFTL employs a probability-based data structure, a bloom filter, for address translation. By leveraging a space-efficient nature of a bloom filter, ProbFTL reduces the amount of DRAM for address translation to 20 percent of the existing techniques. The read latency of ProbFTL is not affected from locality of a workload; ProbFTL guarantees a read amplification factor of 1.1 even under a random read workload. ProbFTL exhibits slightly worse garbage collection efficiency, but its write amplification factor is maintained sufficiently low.

中文翻译:

闪存 SSD 的基于概率的地址转换

由于 NAND 缩放技术的进步,超大规模 SSD(例如, $>$>100 TB) 被引入市场。然而,SSD 容量的快速增加是以更多 DRAM 为代价的,这些 DRAM 驻留在 SSD 控制器中以进行逻辑到物理 (L2P) 地址转换。许多人提出了各种地址转换算法来减少 DRAM,但它们无法提供短的读取延迟,尤其是当工作负载具有弱局部性时。这封信提出了一种新的基于概率的地址转换算法,称为概率FTL. 与保持精确 L2P 映射的现有转换技术相比,ProbFTL 采用基于概率的数据结构,即布隆过滤器进行地址转换。通过利用布隆过滤器的空间效率特性,ProbFTL 将用于地址转换的 DRAM 数量减少到现有技术的 20%。ProbFTL 的读取延迟不受工作负载位置的影响;即使在随机读取工作负载下,ProbFTL 也能保证读取放大系数为 1.1。ProbFTL 的垃圾收集效率稍差,但其写入放大系数保持足够低。
更新日期:2020-07-01
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