In this paper we review a procedure to evaluate the performance of typical analog circuits based on CNTFET, both in SPICE, using ABM library, and in Verilog-A, using a semi-empirical compact model for CNTFETs already proposed by us. The obtained results, with reference to a design of a phase shift oscillator, are the same in static simulations and comparable in dynamic simulations. However using Verilog-A the simulation run time is much shorter and the software is much more concise and clear than schemes using ABM blocks in SPICE. At last we review the procedure for the design of basic and cascode current mirror both in CNTFET and MOS technology. For every simulation we evaluate parameters of merit in order to show the differences between CNTFET and MOS technology.

中文翻译：

---

评论—基于CNTFET的模拟电路的性能评估：评论

在本文中，我们回顾了一种程序，用于评估基于CNTFET的典型模拟电路的性能，无论是在SPICE中使用ABM库，还是在Verilog-A中，使用我们已经提出的CNTFET的半经验紧凑模型。参照相移振荡器的设计，所获得的结果在静态仿真中是相同的，在动态仿真中是可比较的。但是，与在SPICE中使用ABM块的方案相比，使用Verilog-A的仿真运行时间要短得多，软件要简洁得多。最后，我们回顾了CNTFET和MOS技术中基本和共源共栅电流镜的设计过程。对于每个模拟，我们都会评估性能参数，以显示CNTFET和MOS技术之间的差异。