The X-ray SOI pixel sensor onboard the FORCE satellite will be placed in the low earth orbit and will consequently suffer from the radiation effects mainly caused by geomagnetically trapped cosmic-ray protons. Based on previous studies on the effects of radiation on SOI pixel sensors, the positive charges trapped in the oxide layer significantly affect the performance of the sensor. To improve the radiation hardness of the SOI pixel sensors, we introduced a double-SOI (D-SOI) structure containing an additional middle Si layer in the oxide layer. The negative potential applied on the middle Si layer compensates for the radiation effects, due to the trapped positive charges. Although the radiation hardness of the D-SOI pixel sensors for applications in high-energy accelerators has been evaluated, radiation effects for astronomical application in the D-SOI sensors has not been evaluated thus far. To evaluate the radiation effects of the D-SOI sensor, we perform an irradiation experiment using a 6-MeV proton beam with a total dose of $\sim 5\mathrm{krad}$, corresponding to a few tens of years of in-orbit operation. This experiment indicates an improvement in the radiation hardness of the X-ray D-SOI devices. On using an irradiation of 5 krad on the D-SOI device, the energy resolution in the full-width half maximum for the 5.9-keV X-ray increases by $7\pm 2\text{\%}$, and the chip output gain decreases by $0.35\pm 0.09\text{\%}$. The physical mechanism of the gain degradation is also investigated; it is found that the gain degradation is caused by an increase in the parasitic capacitance due to the enlarged buried n-well.

FORCE卫星上的X射线SOI像素传感器将放置在低地球轨道上，因此将受到主要由地磁俘获的宇宙射线质子引起的辐射影响。根据先前对辐射对SOI像素传感器的影响进行的研究，氧化物层中捕获的正电荷会显着影响传感器的性能。为了提高SOI像素传感器的辐射硬度，我们引入了双SOI（D-SOI）结构，该结构在氧化物层中包含一个附加的中间Si层。由于捕获的正电荷，施加在中间Si层上的负电位补偿了辐射效应。尽管已经评估了用于高能加速器的D-SOI像素传感器的辐射硬度，到目前为止，尚未评估D-SOI传感器中用于天文应用的辐射效应。为了评估D-SOI传感器的辐射效果，我们使用6 MeV质子束进行了辐照实验，总剂量为$〜5\mathrm{克拉德}$，对应在轨运行几十年。该实验表明X射线D-SOI装置的辐射硬度得到改善。在D-SOI设备上使用5 krad的辐射后，5.9-keV X射线的全角半最大值处的能量分辨率提高了$7\pm 2\text{％}$，芯片输出增益降低 $0。35\pm 0。09\text{％}$。还研究了增益衰减的物理机制。可以发现，增益的下降是由于埋入的n阱增大而引起的寄生电容的增加所致。