Owing to recent challenges of CMOS manufacturing and power consumption in silicon technologies among alternative technologies, Nanomagnetic logic (NML) is one of the most promising technologies, so it was selected for this study. NML is non-volatile with ultra-low power dissipation that operates at room temperature. This paper aims to propose novel implementation of 2% and 4% multiplexers (MUXs) in NML technology.,The proposed multiplexers in NML technology are verified by HDL-based simulators. In addition, this study estimated area and power dissipation of the proposed design to compare and approve the promising improvements in comparison to other similar NML implementations.,The results show the remarkable improvements in terms of APDP term in comparison to the recent proposed MUXs in NML technology which are reported in Table 2. The proposed implementation of the MUX in NML is designed in three-dimensional layout to improve interconnection complexity which is an integration challenge. Also, by facilitating the routing signals and total wire length needed for clock signals, the negative impact of the power dissipated in clock wires is improved.,These findings would appeal to a broad audience, such as the readership of Microelectronics International Journal. The authors confirm that this work is original and has not been published elsewhere nor is it currently under consideration for publication elsewhere. All authors have approved the paper and agreed with submission to Microelectronics International Journal. The authors have read and have abided by the statement of ethical standards for manuscripts submitted to Microelectronics International Journal. The authors have no conflict of interest to declare.

中文翻译：

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纳米磁逻辑技术中 3D 多路复用器的新实现

由于近期 CMOS 制造和硅技术在替代技术中面临的挑战，纳米磁性逻辑 (NML) 是最有前途的技术之一，因此被选为本研究。NML 是非易失性的，具有超低功耗，可在室温下运行。本文旨在提出 NML 技术中 2% 和 4% 多路复用器 (MUX) 的新实现。NML 技术中提出的多路复用器已通过基于 HDL 的模拟器进行验证。此外，本研究估计了拟议设计的面积和功耗，以比较和批准与其他类似 NML 实现相比的有希望的改进。结果表明，与最近在 NML 中提出的 MUX 相比，APDP 项有显着改进技术见表 2。NML 中 MUX 的拟议实现是在三维布局中设计的，以提高互连复杂性，这是一个集成挑战。此外，通过促进时钟信号所需的路由信号和总导线长度，改善了时钟导线功耗的负面影响。这些发现将吸引广大读者，例如微电子国际期刊的读者。作者确认这项工作是原创的，尚未在其他地方发表，目前也没有考虑在其他地方发表。所有作者均已批准该论文并同意将其提交给 Microelectronics International Journal。作者已阅读并遵守提交给 Microelectronics International Journal 的手稿的道德标准声明。