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On-line self-test mechanism for Dual-Core Lockstep System-on-Chips
Microelectronics Reliability ( IF 1.6 ) Pub Date : 2020-09-01 , DOI: 10.1016/j.microrel.2020.113770
Andrea Floridia , Ernesto Sanchez

Abstract The Dual-Core Lockstep configuration is largely employed in safety-critical System-on-Chips for the sake of compliance with functional safety standards. Such configuration includes two processor cores paired together, always fed with the same identical inputs and their outputs are continuously compared by a set of comparators. However, permanent faults affecting the comparators may invalidate the system functionalities, thus in-field self-test mechanisms are mandatory. In this paper, different in-field self-test solutions are first discussed. Then, a hybrid hardware-software scheme for the on-line testing of the lockstep logic is proposed. Such a solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor. Exhaustive experiments demonstrated that it is possible to achieve a fault coverage of stuck-at faults greater than 99%, while at the same time significantly reduce the area overhead of classical approaches.

中文翻译:

双核锁步片上系统在线自检机制

摘要 为了符合功能安全标准,双核锁步配置主要用于安全关键的片上系统。这种配置包括配对在一起的两个处理器内核,始终以相同的相同输入供电,并且它们的输出由一组比较器连续比较。然而,影响比较器的永久性故障可能会使系统功能失效,因此现场自检机制是强制性的。在本文中,首先讨论了不同的现场自测解决方案。然后,提出了一种用于锁步逻辑在线测试的软硬件混合方案。这种解决方案利用了根据基于软件的自测 (SBST) 方法开发的测试程序,并与专用硬件模块结合使用。这种方法的有效性在 OpenRISC 1200 处理器的修改版本上进行了评估。详尽的实验表明,可以实现大于 99% 的固定故障的故障覆盖率,同时显着减少经典方法的面积开销。
更新日期:2020-09-01
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