Abstract In this paper, we present the fabrication and characterization of gate-all-around (GAA) junctionless (JL) poly-Si nanowire (NW) transistors with a dual-gated configuration, in which a sub-gate is placed over a shorter main-gate in order to control the NW potential for the offset regions between the main-gate and S/D regions. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. Inevitable misalignment of lithographic patterning for the main-gate structure leads to asymmetrical channel offsets between the main-gate to source pad and to drain pad, respectively. That is, the length of un-gated NW close to the source pad differs from that to the drain pad. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end. Such a trend become less profound as the sub-gate bias increases.

中文翻译：

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非对称源极/漏极偏移对双门控多晶硅无结纳米线晶体管工作的影响

摘要 在本文中，我们介绍了具有双栅极配置的环栅 (GAA) 无结 (JL) 多晶硅纳米线 (NW) 晶体管的制造和表征，其中子栅极放置在较短的主栅以控制主栅和 S/D 区域之间偏移区域的 NW 电位。制造的晶体管表现出良好的性能，开/关电流比约为 106，亚阈值摆幅为 76 mV/decade。主栅结构的光刻图案不可避免的未对准分别导致主栅到源极焊盘和漏极焊盘之间的不对称沟道偏移。也就是说，靠近源极焊盘的非栅极NW的长度不同于到漏极焊盘的非栅极NW的长度。笔记的一个重要发现是，当将漏极偏置施加到具有较长沟道偏移的 NW 末端时，漏极电流低于施加到较短末端的电流。随着子栅极偏置的增加，这种趋势变得不那么明显。