The growth in the size of deep neural network (DNN) models poses both computational and memory challenges to the efficient and effective implementation of DNNs on platforms with limited hardware resources. Our work on segmented logarithmic (SegLog) quantization, adopting both base-2 and base-\(\sqrt {2}\) logarithmic encoding, is able to reduce inference cost with a little accuracy penalty. However, weight distribution varies among layers in different DNN models, and requires different base-2 : base-\(\sqrt {2}\) ratios to reach the best accuracy. This means different hardware designs for the decoding and computing parts are required. This paper extends the idea of SegLog quantization by using layer-wise base-2 : base-\(\sqrt {2}\) ratio on weight quantization. The proposed base-reconfigurable segmented logarithmic (BRSLog) quantization is able to achieve 6.4x weight compression with 1.66% Top-5 accuracy drop on AlexNet at 5-bit resolution. An arithmetic element supporting BRSLog-quantified DNN inference is proposed to adapt to different base-2 : base-\(\sqrt {2}\) ratios. With \(\sqrt {2}\) approximation, the resource-consuming multipliers can be replaced by shifters and adders with only 0.54% accuracy penalty. The proposed arithmetic element is simulated in UMC 55nm Low Power Process, and it is 50.42% smaller in area and 55.60% lower in power consumption than the widely-used 16-bit fixed-point multiplier. Compared with equivalent SegLog arithmetic element designed for fixed base-2 : base-\(\sqrt {2}\) ratio, the base-reconfigurable part only increases the area by 22.96 μm² and energy cost by 2.6 μW.

深度神经网络（DNN）模型的规模不断增长，在硬件资源有限的平台上高效有效地实施DNN带来了计算和内存方面的挑战。我们采用base-2和base- \（\ sqrt {2} \）对数编码的分段对数（SegLog）量化工作，可以降低推理成本，同时降低精度。但是，权重分布在不同DNN模型中的各层之间会有所不同，并且需要不同的base-2：base- \（\ sqrt {2} \）比率才能达到最佳精度。这意味着需要用于解码和计算部分的不同硬件设计。本文通过使用逐层的base-2扩展了SegLog量化的思想：base- \（\ sqrt {2} \）权重比。所提出的基本可重新配置的分段对数（BRSLog）量化能够以5位分辨率在AlexNet上实现6.4倍权重压缩，而Top-5精度下降1.66％。提出了一种支持BRSLog量化DNN推理的算术元素，以适应不同的base-2：base- \（\ sqrt {2} \）比率。利用\（\ sqrt {2} \）近似值，可以用移位器和加法器代替耗资源的乘法器，而精度损失仅为0.54％。拟议的算术元素在UMC 55nm低功耗工艺中进行了仿真，与广泛使用的16位定点乘法器相比，其面积减小了50.42％，功耗降低了55.60％。与为固定base-2设计的等效SegLog算术元素相比：base-\（\ SQRT {2} \）比率，基部可重构部分仅由22.96μ增加面积中号² 2.6μW和能源成本。