The purpose of this paper is to design a kernel convolution processor. High-speed image processing is a challenging task for real-time applications such as product quality control of manufacturing lines. Smart image sensors use an array of in-pixel processors to facilitate high-speed real-time image processing. These sensors are usually used to perform the initial low-level bulk image filtering and enhancement.,In this paper, using pulse-width modulated signals and regular nearest neighbor interconnections, a convolution image processor is presented. The presented processor is not only capable of processing arbitrary size kernels but also the kernel coefficients can be any arbitrary positive or negative floating number.,The performance of the proposed architecture is evaluated on a Xilinx Virtex-7 field programmable gate array platform. The peak signal-to-noise ratio metric is used to measure the computation error for different images, filters and illuminations. Finally, the power consumption of the circuit in different operating conditions is presented.,The presented processor array can be used for high-speed kernel convolution image processing tasks including arbitrary size edge detection and sharpening functions, which require negative and fractional kernel values.

中文翻译：

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用于视觉传感器中并行内核卷积的基于带符号脉冲序列的图像处理器阵列

本文的目的是设计一个内核卷积处理器。高速图像处理对于生产线的产品质量控制等实时应用来说是一项具有挑战性的任务。智能图像传感器使用一系列像素内处理器来促进高速实时图像处理。这些传感器通常用于执行初始的低级批量图像滤波和增强。,在本文中，使用脉宽调制信号和规则最近邻互连，提出了卷积图像处理器。所提出的处理器不仅能够处理任意大小的内核，而且内核系数可以是任意任意正浮点数或负浮点数。所提出架构的性能在 Xilinx Virtex-7 现场可编程门阵列平台上进行了评估。峰值信噪比度量用于测量不同图像、过滤器和照明的计算误差。最后，给出了电路在不同工作条件下的功耗。所提出的处理器阵列可用于高速内核卷积图像处理任务，包括任意大小的边缘检测和锐化功能，这些任务需要负核值和分数核值。