The purpose of this paper is to investigate the effect of high-k material HfO2 as a buffer layer for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate.,RF-sputtered Pb[Zr0.35Ti0.65]O3 or (PZT) and plasma-enhanced atomic layer deposited HfO2 films were selected as the ferroelectric and high-k buffer layer, respectively, for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate. Multiple angle ellipsometry and X-ray diffraction analysis was carried out to obtain the crystal orientation, refractive index and absorption coefficient parameters of the deposited/annealed films. In the different range of annealing temperature, the refractive index was observed in the range of 2.9 to 2 and 1.86 to 2.64 for the PZT and HfO2 films, respectively,Electrical and ferroelectric properties of the dielectric and ferroelectric films and their stacks were obtained by fabricating the metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal, metal/insulator/silicon and MFeIS capacitor structures. A closed hysteresis loop with remnant polarization of 4.6 µC/cm2 and coercive voltage of 2.1 V was observed in the PZT film annealed at 5000 C. Introduction of HfO2 buffer layer (10 nm) improves the memory window from 5.12 V in MFeS to 6.4 V in MFeIS structure with one order reduction in the leakage current density. The same MFeS device was found having excellent fatigue resistance property for greater than 1010 read/write cycles and data retention time more than 3 h.,The MFeIS structure has been fabricated with constant PZT thickness and varied buffer layer (HfO2) thickness. Electrical characteristics shows the improved leakage current and memory window in the MFeIS structures as compared to the MFeS structures. Optimized MFeIS structure with 10-nm buffer layer shows the excellent ferroelectric properties with endurance greater than E10 read/write cycles and data retention time higher than 3 h. The above properties indicate the MFe(100 nm)I(10 nm)S gate stack as a potential candidate for the FeFET-based nonvolatile memory applications.

中文翻译：

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钙钛矿Pb[Zr0.35Ti0.65]O3/HfO2铁电介质复合膜在Si衬底上的集成

本文的目的是研究高 k 材料 HfO2 作为缓冲层在 Si (100) 衬底上制造金属-铁电-绝缘体-硅 (MFeIS) 结构的效果。,RF 溅射 Pb[Zr0.分别选择 35Ti0.65]O3 或 (PZT) 和等离子体增强原子层沉积的 HfO2 薄膜作为铁电和高 k 缓冲层，用于在 Si 上制造金属-铁电-绝缘体-硅 (MFeIS) 结构（ 100) 基材。进行多角椭偏仪和X射线衍射分析以获得沉积/退火薄膜的晶体取向、折射率和吸收系数参数。在不同的退火温度范围内，PZT 和 HfO2 薄膜的折射率分别在 2.9 到 2 和 1.86 到 2.64 的范围内，通过制造金属/铁电/硅 (MFeS)、金属/铁电/金属、金属/绝缘体/硅和 MFeIS 电容器结构，获得了电介质和铁电薄膜及其叠层的电和铁电特性。在 5000°C 下退火的 PZT 薄膜中观察到具有 4.6 µC/cm2 残余极化和 2.1 V 矫顽力的闭合磁滞回线。 HfO2 缓冲层（10 nm）的引入将 MFeS 中的 5.12 V 存储器窗口提高到 6.4 V在 MFeIS 结构中，漏电流密度降低了一个数量级。发现相同的 MFeS 器件具有超过 1010 次读/写循环和超过 3 小时的数据保留时间的优异抗疲劳性能。已制造具有恒定 PZT 厚度和不同缓冲层 (HfO2) 厚度的 MFeIS 结构。电气特性表明，与 MFeS 结构相比，MFeIS 结构中改进的漏电流和存储窗口。具有 10 nm 缓冲层的优化 MFeIS 结构显示出优异的铁电性能，耐久性大于 E10 读/写循环，数据保留时间大于 3 小时。上述特性表明 MFe(100 nm)I(10 nm)S 栅极堆叠是基于 FeFET 的非易失性存储器应用的潜在候选。