Purpose

The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V.

Design/methodology/approach

In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates.

Findings

The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP.

Originality/value

In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

中文翻译：

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通过探索45nm CMOS工艺中的新“或”门设计省电的Kogge–Stone加法器

目的

这项工作的目的是减少KSA的功耗并改善数据路径应用的PDP。在数字超大规模集成系统中，两个数字的加法是基本功能之一。该算术函数用于现代数字信号处理器和微处理器中。这些处理器的运行速度取决于算术函数的计算。大多数数据路径元素的速度计算模块是加法器。在本文中，Kogge-Stone加法器（KSA）是使用XOR，AND和提出的OR门设计的。所提出的“或”门具有较少的功耗，这是因为晶体管的数量较少。在算术逻辑电路中，功率，延迟和功率延迟乘积（PDP）被视为重要参数。与常规的互补金属氧化物半导体（CMOS）或门和预先存在的逻辑样式相比，为所建议的或门报告的延迟较小。建议的电路在功率，延迟和PDP方面进行了优化。为了分析KSA的性能，使用了广泛的Cadence Virtuoso仿真。从基于45 nm CMOS工艺的仿真结果可以看出，该设计在1.1 V电压下的功耗为688.3 nW，延迟为0.81 ns，PDP为0.55 fJ。

设计/方法/方法

本文提出了一种新的或门电路。使用XOR，AND和提议的OR门设计KSA。

发现

所提出的“或”门具有较少的功耗，这是因为晶体管的数量较少。与传统的CMOS或门和先前存在的逻辑样式相比，为所建议的或门报告的延迟较小。建议的电路在功率，延迟和PDP方面进行了优化。

创意/价值

在算术逻辑电路电源中，延迟和PDP被视为重要参数。本文提出了一种新的或门电路。与传统的KSA相比，使用建议的或门设计的KSA的功耗非常小。仿真结果表明，所提出的KSA的性能得到了改善，适合于高速应用。