Purpose

Quantum-dot cellular automata (QCA) is a promising technology, which seems to be the prospective substitute for complementary metal-oxide semiconductor (CMOS). It is a high speed, high density and low power paradigm producing efficient circuits. These days, most of the smart devices used for computing, make use of random access memory (RAM). To enhance the performance of a RAM cell, researchers are putting effort to minimize its area and access time. Multilayer structures in QCA framework are area efficient, fast and immune to the random interference. Unlike CMOS, QCA multilayer architectures can be designed using active components on different layers. Thus, using multilayer topology in the design of a RAM cell, which is not yet reported in the literature can improve the performance of RAM and hence, the computing device. This paper aims to present the modular design of RAM cell with multilayer structures in the QCA framework. The fundamental modules such as XOR gate, 2:1 multiplexer and D latch are proposed here using multilayer formations with the goal of designing a RAM cell with the provision of read, write, set and reset control.

Design/methodology/approach

All the modules used to design a RAM cell are designed using multilayer approach in QCA framework.

Findings

The proposed multilayer RAM cell is optimized and has shown an improvement of 20% in cell count, 30% in area, 25% in area latency product and 48.8% in cost function over the other efficient RAM designs with set/reset ability reported earlier. The proposed RAM cell is further analyzed for the fault tolerance and power dissipation.

Research limitations/implications

Due to the multilayer structure, the complexity of the circuit enhances which can be eliminated using simple architectures.

Originality/value

The performance metrics and results obtained establish that the multilayer approach can be implemented in the QCA circuit to produce area efficient and optimized sequential circuits such as a latch, flip flop and memory cells.

中文翻译：

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QCA框架中高效多层RAM单元的设计

目的

量子点自动机（QCA）是一项很有前途的技术，它似乎是互补金属氧化物半导体（CMOS）的潜在替代品。它是产生高效率电路的高速，高密度和低功耗范例。如今，大多数用于计算的智能设备都利用随机存取存储器（RAM）。为了提高RAM单元的性能，研究人员正在尽最大努力减小其面积和访问时间。QCA框架中的多层结构具有区域高效，快速且不受随机干扰的影响。与CMOS不同，可以使用不同层上的有源组件来设计QCA多层体系结构。因此，在RAM单元的设计中使用多层拓扑结构（这在文献中尚未报道）可以改善RAM的性能，从而改善计算设备的性能。本文旨在介绍QCA框架中具有多层结构的RAM单元的模块化设计。此处提出了使用多层结构的基本模块，例如XOR门，2：1多路复用器和D锁存器，目的是设计一种具有读，写，设置和复位控制功能的RAM单元。

设计/方法/方法

用于设计RAM单元的所有模块均在QCA框架中使用多层方法进行设计。

发现

所提出的多层RAM单元经过了优化，与先前报道的具有置位/复位功能的其他高效RAM设计相比，其单元数，面积30％，面积延迟乘积25％和成本函数提高了20％。对所提出的RAM单元进行了进一步的容错和功耗分析。

研究局限/意义

由于采用了多层结构，电路的复杂性增加了，可以使用简单的架构将其消除。

创意/价值

获得的性能指标和结果表明，可以在QCA电路中实施多层方法，以产生面积有效且优化的时序电路，例如锁存器，触发器和存储单元。