Purpose

Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process.

Design/methodology/approach

Initially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved.

Findings

The designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW.

Research limitations/implications

A time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC.

Social implications

The designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society.

Originality/value

The implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power.

中文翻译：

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基于控制器的全数字锁相环（ADPLL）的CMOS实现

目的

生物医学射频（RF）收发器需要小型化的形式，并具有较长的电池寿命和低功耗。402-405 MHz频率范围内的医疗植入物通信服务（MICS）频带被广泛用于医疗RF收发器，因为MICS频带信号具有合理的传播特性并适合于获得良好的结果。医疗设备的射频前端的实现面临许多挑战，因为这些挑战表明功耗很低。尤其是，锁相环是RF前端最关键的模块之一。本文的目的是在45 nm CMOS工艺中设计基于控制器的全数字锁相环（ADPLL）。

设计/方法/方法

最初，设计了一种开环架构相位频率检测器（PFD）。然后，基于差分缓冲器的概念，采用电容升压技术构建了一个差分环形振荡器（RO）。此后，通过适当的数学建模来构建频率控制器模块，该数学模型可以完成环路滤波器的工作，其作用类似于相位内插器。频率控制器块有调谐寄存器块，调谐字寄存器。调谐块是使用金属氧化物半导体（MOS）盖构建的。最后，完成所有模块的集成，并实现了锁定在402 MHz的ADPLL架构。

发现

设计的PFD无死区，工作频率为1 GHz。差分RO在495 MHz处振荡。拟议的ADPLL在402 MHz下工作，在1-MHz偏移下测得的相位噪声为-98.36。该ADPLL的均方根抖动为4.626 ps，总功耗为216.5 µW。

研究局限/意义

采用45 nm / 0.68 V CMOS技术设计了一种无时间数字转换器（TDC）的基于控制器的低功耗ADPLL，涵盖了生物医学应用的MICS频带。本草案中提出的ADPLL使用具有电容增强技术的差分振荡器，该技术将工作电压降低至0.68V。该ADPLL的带宽为20 kHz，在20 MHz的参考频率下工作，消耗的功率为216.5 µW，同时产生输出频率为402 MHz。调谐范围是375至428 MHz。频率控制器模块在1 MHz时具有−98.36 dbc / Hz的相位噪声，取代了TDC的使用。

社会影响

设计的ADPLL必将为生物医学领域的更大研究领域铺平道路。该ADPLL是结合了电子学和生物医学领域的独特组合。设计的ADPLL本身是生物医学领域的更广泛应用，将对社会产生积极影响。

创意/价值

使用电容性升压技术实现开环PFD和RO是一种独特的组合。频率控制器模块可以很好地理解这一点，该模块消除了TDC的使用，并且可以用作相位内插器。适应MICS频段应用的ADPLL的整个设计经过精心设计，可在低功耗下工作。