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Design of hardened flip-flop using Schmitt trigger-based SEM latch in CNTFET technology
Circuit World ( IF 0.8 ) Pub Date : 2020-06-01 , DOI: 10.1108/cw-10-2019-0141
Divya Madhuri Badugu , Sunithamani S. , Javid Basha Shaik , Ramesh Kumar Vobulapuram

Purpose

The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).

Design/methodology/approach

To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset.

Findings

To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions.

Originality/value

The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.



中文翻译:

使用CNTFET技术中基于施密特触发器的SEM锁存器设计的增强型触发器

目的

本文的目的是设计一种使用碳纳米管场效应晶体管(CNTFET)的新型硬化触发器。

设计/方法/方法

为了设计所提出的触发器,已经使用了基于施密特触发器的软错误屏蔽和未强化的锁存器。在提出的设计中,使用了新颖的机制,即磁滞特性来增强单事件心烦的硬度。

发现

为了获得仿真结果,所有提出的电路都在带有集成电路增强软件的Hewlett仿真程序中进行了广泛的仿真。此外,将所提出的锁存器的结果与常规锁存器进行比较以显示性能的提高。应当注意,与常规锁存器相比,在功耗,面积和功率延迟乘积方面,所提出的锁存器分别显示出高达25.8%,51.2%和17.8%的性能改进。另外,可以看到,所提出的触发器的仿真结果证实了其相应功能的正确性。

创意/价值

介绍了利用基于ST的SEM锁存器的新型硬化触发器。与现有触发器相比,该触发器显着提高了性能和可靠性。

更新日期:2020-06-01
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