The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells.,This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue.,The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart.,Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit.,GNRFET devices are suitable for implementing low power and high density SRAM cell.,The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices.,This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

中文翻译：

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采用多VT技术的无读干扰稳定低功耗高密度GNRFET 6T SRAM

使用具有多阈值技术的 GNRFET 器件可以提高传统 6T SRAM 单元的性能。所提出的单元显示出在 325 mV 的最小电源电压下运行的强大能力，而传统的 Si-CMOS 6 T SRAM 无法在低于 725 mV 的情况下运行，这导致了可接受的故障率。基于金属氧化物半导体）的 6 T SRAM 单元面临着积极缩小规模的固有限制。因此，需要为传统单元提出替代方案。本研究旨在使用双阈值技术、器件尺寸、在 GNRFET 技术的工艺变化下优化电源电压来提高传统 6T SRAM 单元的性能。通过解决半选择问题可以进一步提高性能。基于 GNRFET 的 6T SRAM 单元表明，它能够在工艺、电压和温度 (PVT) 变化下持续提高性能，明显优于其对应的 CMOS。GNRFET 的纳米材料制造技术处于早期阶段；因此，不同的晶体管模型可用于评估未来 GNRFET 电路的参数。GNRFET 器件适用于实现低功耗和高密度 SRAM 单元。传统的 Si-CMOS 6 T SRAM 单元是核心组件，用作计算机系统组织、移动电话和其他数据存储设备中高速缓存中的大容量存储元件。本文提出了一种新方法来实现基于 GNRFET 的 6T SRAM 单元的替代设计，该单元具有也支持工艺变化的掺杂储层。此外，多阈值技术优化了所提议电池的性能。所提出的设计提供了一种在考虑边缘粗糙度的工艺变化下分析基于 GNRFET 的 SRAM 的延迟和功率的方法，并为未来的单元提供设计和制造见解。