A 4- bit reusable stage based asynchronous binary search analog to digital converter (ADC) with a smart switching network, and reduced comparator count is presented in this paper. The proposed ADC uses asynchronous logic to activate comparators sequentially while switching network is used to provide reference voltages for selected comparators. In the extended version, the 6-bit ADC is designed using only \((\mathrm{N}+1)\) comparators instead of \(2^{(N)}-1\) and (2N − 1) as used in conventional approach. The simulation results of 4 bit ADC confirms that the design achieves conversion speed of 500 MSPS with power consumption of 1.63 mW when operated on 1.8 V supply with SNR, SFDR and ENOB as 22.5 dB, 32.4 dBc and 3.8 bits while for 6 bit the SNR, SFDR and ENOB are 34.96 dB, 42 dBc and 5.56 bits respectively with 0.35 mW of power dissipation. The Walden FOM for proposed 4 bit and 6 bit ADC design are 0.21 pJ/conversion-step and 24.7 fJ/conversion-step respectively.

本文提出了一种具有智能开关网络的基于4位可重用级的异步二进制搜索模数转换器（ADC），并减少了比较器的数量。拟议的ADC使用异步逻辑依次激活比较器，同时使用开关网络为选定的比较器提供参考电压。在扩展版本中，仅使用\（（\ mathrm {N} +1）\）比较器而不是\ {2 ^ {（N）}-1 \）设计6位ADC和（2N-1），在常规方法中使用。4位ADC的仿真结果证实，该设计在1.8 V电源下工作时具有SNR，SFDR和ENOB分别为22.5 dB，32.4 dBc和3.8位的情况下，实现了500 MSPS的转换速度和1.63 mW的功耗，而对于6位SNR ，SFDR和ENOB分别为34.96 dB，42 dBc和5.56位，功耗为0.35 mW。建议的4位和6位ADC设计的Walden FOM分别为0.21 pJ /转换步长和24.7 fJ /转换步长。