Reducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope (SS), and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account the problems associated with their inverse current due to their intrinsic p-i-n diode. In this article, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially at medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs.

中文翻译：

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使用隧道晶体管设计能量回收逻辑电路

降低电源电压是降低功耗的有效方法，但它会大大降低 CMOS 电路的速度。由于频率限制，这意味着在许多应用中可以将电源电压降低到多低的限制。特别是，在低压绝热电路（另一种众所周知的节能技术）的背景下，不可能获得令人满意的功率-速度权衡。隧道场效应晶体管 (TFET) 在静态逻辑实现中的低电源电压下表现优于 CMOS，由于其陡峭的亚阈值斜率 (SS) 操作，并且具有结合低电压和绝热的潜力。据我们所知，使用 TFET 报告的绝热电路拓扑没有考虑由于其固有的 pin 二极管而与反向电流相关的问题。在本文中，我们提出了针对此问题的解决方案，证明与原始修改相比，所提出的修改可以显着提高功率/节能方面的性能，尤其是在中低频方面。此外，我们评估了所提出的 TFET 绝热电路相对于它们的静态实现的相对优势，证明这些优势比 FinFET 晶体管设计更大。尤其是中低频。此外，我们评估了所提出的 TFET 绝热电路相对于它们的静态实现的相对优势，证明这些优势比 FinFET 晶体管设计更大。尤其是中低频。此外，我们评估了所提出的 TFET 绝热电路相对于它们的静态实现的相对优势，证明这些优势比 FinFET 晶体管设计更大。