This paper presents a fully integrated 10-bit 100 MS/s successive approximation register (SAR) ADC for the high energy physics experiments. The ADC uses a non-binary weighted capacitor digital-to-analog converter (C-DAC) network and a hybrid capacitor switching procedure to increase conversion accuracy and speed. A metastability elimination technique is employed to avoid comparator metastability, and then reduce the conversion error rate (CER) at high-speed asynchronous operations. The full custom static logic is used to improve the radiation hardness. The ADC was designed and fabricated in a 40 nm CMOS process. It occupies 0.078 mm² active area, including a reference generator, with a core area of 0.037 mm². The measured ADC core power consumption and the total power consumption are 1.32 mW and 8.5 mW respectively, including the reference generator at a 1.1 V supply. The resulting figure-of-merit (FOM), for sampling rate 100 MS/s, is 130 fJ/conversion-step. It achieves a good dynamic performance with $\sim$9.3-bit effective number of bits (ENOB) at 100 MS/s with 14.97 MHz input signal. The measured spurious free dynamic range (SFDR), total harmonic distortion (THD) and signal-to-noise ratio (SNR) are 72.6 dB, −69.2 dB, 58.3 dB, respectively. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.62/−0.4 LSB and +0.67/−0.54 LSB respectively.

本文提出了一种用于高能物理实验的完全集成的10位100 MS / s逐次逼近寄存器（SAR）ADC。ADC使用非二进制加权电容器数模转换器（C-DAC）网络和混合电容器开关程序来提高转换精度和速度。采用亚稳态消除技术来避免比较器亚稳态，然后降低高速异步操作时的转换错误率（CER）。完整的自定义静态逻辑用于提高辐射硬度。ADC是在40 nm CMOS工艺中设计和制造的。它占据了0.078 mm ^2的有效面积，包括一个参考发生器，其核心面积为0.037 mm ²。测得的ADC内核功耗和总功耗分别为1.32 mW和8.5 mW，包括在1.1 V电源下的基准发生器。对于100 MS / s的采样率，所得的品质因数（FOM）为130 fJ /转换步长。它具有良好的动态性能$〜$输入信号为14.97 MHz时100 MS / s时的9.3位有效位数（ENOB）。测得的无寄生动态范围（SFDR），总谐波失真（THD）和信噪比（SNR）分别为72.6 dB，-69.2 dB和58.3 dB。测得的微分非线性（DNL）和积分非线性（INL）分别为+ 0.62 / -0.4 LSB和+ 0.67 / -0.54 LSB。