This paper presents a framework for complete simulation and verification of Serial Digital Interface (SDI) video using a verilog test-bench and geared toward FPGAs. This framework permits simulating the entire process: from test video signal generation to protocol verification in the FPGA which implements the Device Under Test (DUT). The novelty in the design is the combination of a customized test video signal generator with an implementation clone of DUT transceiver for in-depth protocol debugging. Identical input test patterns of the video protocol under test are generated and fed to DUT for verification. Thus, the model not only permits to evaluate the SDI transport layer but also validates the implementation at ultra low pixel level of the video format. This approach provides two advantages: cost saving in terms of additional lab test equipment and delivering all-in-one test solution to verify design and implementation. A practical implementation using a test example of a macroblock processing chain using SDI video interface shows the viability of the proposed framework for video protocol testing.

中文翻译：

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用于SDI流验证的基于FPGA的新型测试平台框架

本文提出了一个框架，该框架可使用Verilog测试平台并针对FPGA来对串行数字接口（SDI）视频进行完整的仿真和验证。该框架允许模拟整个过程：从测试视频信号生成到FPGA中的协议验证，该FPGA实现了被测设备（DUT）。该设计的新颖之处在于将定制的测试视频信号发生器与DUT收发器的实现克隆相结合，以进行深入的协议调试。生成与被测视频协议相同的输入测试模式，并将其输入到DUT以进行验证。因此，该模型不仅可以评估SDI传输层，而且可以在视频格式的超低像素级别验证其实现。这种方法具有两个优点：通过额外的实验室测试设备节省成本，并提供多合一的测试解决方案来验证设计和实施。使用SDI视频接口的宏块处理链的测试示例的实际实现显示了所提出的视频协议测试框架的可行性。