Increased feature scaling to achieve high performance of miniaturized circuits has increased concerns related to their reliability as smaller circuits age faster. This means that more computational errors due to defects are expected in modern nanoscale circuits. Logic implication checking is a concurrent error detection technique that can detect a partial number of these errors at reduced hardware costs. However, implications-based error detection suffers from a low error coverage in FPGA-implemented circuits making it useless for any practical purposes. In this paper, we identify the reasons for a degraded performance of implication checking in FPGAs and propose multi-wire implications towards achieving better error detection probabilities (P_detection). The addition of multi-wire implications boosts the number of candidate implications and contributes more valuable implications thereby increasing the average P_detection achieved by almost 1.7 times at around 65.7% with only a 25% increase in the average area overhead for the given test circuits. Moreover, we show that the efficiency of implications in detecting errors not only varies from one circuit to another but that it also depends largely on the specific implementation of the circuit under test as supported through analytic analyses and comparisons between experimental results obtained from hardware fault injection of the implemented circuits and fault simulations on corresponding circuit netlists.

随着小型电路老化的加快，为实现微型电路的高性能而增加的特征缩放比例也增加了对其可靠性的关注。这意味着在现代的纳米级电路中，由于缺陷会导致更多的计算错误。逻辑隐含检查是一种并行错误检测技术，可以降低硬件成本来检测这些错误的一部分。但是，基于含义的错误检测在FPGA实现的电路中具有较低的错误覆盖率，因此无法用于任何实际目的。在本文中，我们确定了FPGA中含义检查性能下降的原因，并提出了多线含义，以实现更好的错误检测概率（P_检测）。）。多线影响的增加增加了候选影响的数量，并贡献了更有价值的影响，从而使所获得的平均P_检测率提高了近1.7倍，约为65.7％，而给定测试电路的平均面积开销仅增加了25％。此外，我们表明，检测错误的含义效率不仅在一个电路与另一个电路之间有所不同，而且还很大程度上取决于通过分析分析和比较从硬件故障注入获得的实验结果所支持的被测电路的具体实现。相应电路网表上已实现的电路和故障仿真的信息。