Abstract UMOSFET on-resistances have been dramatically improved in recent decades with the miniaturization of cell size by innovations in the fabrication process. However, with miniaturization, failure in the gate oxide, large deviations in the threshold voltage and reductions in avalanche capability have emerged as design problems for mass production. In particular, threshold voltage increase have appeared with the introduction of a trench source contact. The source contact trench and MOS gate trench are fabricated next to each other with a narrow silicon mesa region, and the voltage increase appear when the silicon mesa width becomes narrower than 80 nm. So far, it appears that the P+ layer dopant in the contact sidewall diffuses toward the gate oxide and the channel doping increases, which causes the increase in the threshold voltage Vth. We analyzed the distribution of Vth at the wafer level/shot level and found for the first time that the increase in Vth is caused by the punch-through effect from the channel depletion layer to the contact P+ layer, and thus, sidewall dopant diffusion will not affect the increase in Vth. We established an analytical model for the increase in Vth. Our model showed that for the field plate type UMOSFET with a shorter gate contact length, not only is there a increase in Vth, but also it is difficult to control Vth using the conventional channel implantation method.

中文翻译：

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单元尺寸减小对 UMOSFET 阈值电压的影响

摘要 近几十年来，随着制造工艺的创新，随着单元尺寸的小型化，UMOSFET 的导通电阻得到了显着改善。然而，随着小型化、栅极氧化层失效、阈值电压的大偏差和雪崩能力的降低已经成为大规模生产的设计问题。特别是，随着沟槽源接触的引入，阈值电压已经出现。源极接触沟槽和MOS栅极沟槽相邻制作，硅台面区域较窄，当硅台面宽度小于80nm时出现电压升高。目前看来，接触侧壁中的P+层掺杂物向栅氧化层扩散，沟道掺杂增加，导致阈值电压Vth升高。我们分析了Wafer level/shot level的Vth分布，首次发现Vth的增加是由沟道耗尽层到接触P+层的穿通效应引起的，因此侧壁掺杂扩散将不影响 Vth 的增加。我们建立了 Vth 增加的分析模型。我们的模型表明，对于栅极接触长度较短的场板型 UMOSFET，不仅 Vth 增加，而且使用传统的沟道注入方法难以控制 Vth。我们建立了 Vth 增加的分析模型。我们的模型表明，对于栅极接触长度较短的场板型 UMOSFET，不仅 Vth 增加，而且使用传统的沟道注入方法难以控制 Vth。我们建立了 Vth 增加的分析模型。我们的模型表明，对于栅极接触长度较短的场板型 UMOSFET，不仅 Vth 增加，而且使用传统的沟道注入方法难以控制 Vth。