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Efficient Computation Techniques and Hardware Architectures for Unitary Transformations in Support of Quantum Algorithm Emulation
Journal of Signal Processing Systems ( IF 1.8 ) Pub Date : 2020-07-14 , DOI: 10.1007/s11265-020-01569-4
Naveed Mahmud , Bennett Haase-Divine , Annika Kuhnke , Apurva Rai , Andrew MacGillivray , Esam El-Araby

As the development of quantum computers progresses rapidly, continuous research efforts are ongoing for simulation and emulation of quantum algorithms on classical platforms. Software simulations require use of large-scale, costly, and resource-hungry supercomputers, while hardware emulators make use of fast Field-Programmable-Gate-Array (FPGA) accelerators, but are limited in accuracy and scalability. This work presents a cost-effective FPGA-based emulation platform that demonstrates improved scalability, accuracy, and throughput compared to existing FPGA-based emulators. In this work, speed and area trade-offs between different proposed emulation architectures and computation techniques are investigated. For example, stream-based computation is proposed that greatly reduces resource utilization, improves system scalability in terms of the number of emulated quantum bits, and allows for dynamically changing algorithm inputs. The proposed techniques assume that the unitary transformation of the quantum algorithm is known, and the matrix values can be pre-computed or generated dynamically. 32-bit floating-point precision is used for high accuracy and the architectures are fully pipelined to ensure high throughput. As case studies for emulation, the quantum Fourier transform and Grover’s search algorithms are investigated and quantum circuits for multi-pattern Grover’s search are also proposed. Experimental evaluation and analysis of the emulation architectures and computation techniques are provided for the investigated quantum algorithms. The emulation framework is prototyped on a high-performance reconfigurable computing (HPRC) system and the results show quantitative improvement over existing FPGA-based emulators.



中文翻译:

支持量子算法仿真的Unit变换的高效计算技术和硬件架构

随着量子计算机的发展迅速,正在进行持续的研究工作以在经典平台上进行量子算法的仿真和仿真。软件仿真需要使用大型,昂贵且耗费资源的超级计算机,而硬件仿真器则使用快速的现场可编程门阵列(FPGA)加速器,但准确性和可扩展性受到限制。这项工作提出了一个具有成本效益的基于FPGA的仿真平台,与现有的基于FPGA的仿真器相比,该平台展示了更高的可扩展性,准确性和吞吐量。在这项工作中,研究了不同的拟议仿真体系结构和计算技术之间的速度和面积之间的折衷。例如,提出了基于流的计算,该计算大大降低了资源利用率,就仿真量子位数的数量而言,提高了系统可伸缩性,并允许动态更改算法输入。所提出的技术假定量子算法的the变换是已知的,并且矩阵值可以被预先计算或动态地生成。使用32位浮点精度以实现高精度,并且对体系结构进行了完全流水线处理以确保高吞吐量。作为仿真的案例研究,研究了量子傅立叶变换和Grover搜索算法,并提出了用于多模式Grover搜索的量子电路。为研究的量子算法提供了仿真体系结构和计算技术的实验评估和分析。

更新日期:2020-07-15
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