Static random access memory– (SRAM) based field programmable gate arrays (FPGAs) are currently facing challenges of limited capacity and high leakage power. To solve this problem, non-volatile memory (NVM) is proposed as the alternative to build non-volatile FPGAs (NVFPGAs). Even though the feasibility of NVFPGA has been confirmed, the utilization of multiple level cells (MLCs) has not been fully exploited yet. In this article, we study architecture of MLC-based NVFPGAs, and propose five cluster structures. To give detailed comparisons and extensive discussions, we conduct experiments for area, performance and leakage power evaluation. Based on explorations of the characteristics of MLC-based NVFPGAs, we further present MLC-aware timing-driven packing method to improve delay. In critical paths, our proposed method reduces the overhead of the additional delay in slow MLC cells. Experiments show that, compared to SRAM-based FPGAs, the proposed architecture with the proposed CAD flow can reduce the area, critical path delay and leakage power by 31%, 10%, and 95%, respectively.

中文翻译：

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将多级单元应用于非易失性 FPGA

基于静态随机存取存储器 (SRAM) 的现场可编程门阵列 (FPGA) 目前面临容量有限和高泄漏功率的挑战。为了解决这个问题，提出了非易失性存储器 (NVM) 作为构建非易失性 FPGA (NVFPGA) 的替代方案。尽管 NVFPGA 的可行性已得到证实，但多层单元 (MLC) 的利用尚未得到充分利用。在本文中，我们研究了基于 MLC 的 NVFPGA 的架构，并提出了五种集群结构。为了进行详细的比较和广泛的讨论，我们进行了面积、性能和泄漏功率评估的实验。在探索基于 MLC 的 NVFPGA 特性的基础上，我们进一步提出了 MLC 感知的时序驱动打包方法来改善延迟。在关键路径中，我们提出的方法减少了慢 MLC 单元中额外延迟的开销。实验表明，与基于 SRAM 的 FPGA 相比，所提出的架构与所提出的 CAD 流程可以分别减少 31%、10% 和 95% 的面积、关键路径延迟和泄漏功率。