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On the design of the channel region in 4H-SiC JBS diode through an analytical model of the potential barrier
Mathematics and Computers in Simulation ( IF 4.4 ) Pub Date : 2021-05-01 , DOI: 10.1016/j.matcom.2020.07.008
Luigi Di Benedetto , Gian Domenico Licciardo , Alfredo Rubino

Abstract In this paper, we propose a tool for the design of 4H-polytype Silicon Carbide Junction Barrier Schottky, JBS, diodes, which are promising devices for their low on-state resistance and their high blocking voltage. Our tool calculates the width of the channel region in terms of the geometrical and physical parameters and of the doping concentration in order that the device shows forward electrical characteristics similar to that of Schottky Barrier Diode. Their operating principle is defined by the control of the flow of electron carriers through a potential barrier, which is located in the n-type region under the Schottky metal contact surrounded by the p + -type regions. Indeed, if the electric fields of the p + -n junctions extend for the whole channel region under equilibrium conditions, the height of the induced potential barrier can be higher than that of the conventional Schottky built-in potential and can affect the electrical characteristics of the device, for example increasing the turn-on voltage. Although they have been firstly developed in Silicon technology, 4H-SiC JBS diodes are easier to fabricate because the electric fields of 4H-SiC p–n junctions have a wider space charge region for the same values of the doping concentrations with respect to Si JBS devices, resulting in a more relaxed design constrain of the channel geometry. Our analytical model can calculate the potential barrier height as function of the geometrical and physical parameters of the device and can evaluate the maximum channel width for which the potential barrier is higher than Schottky built-in voltage. The analytical results are compared through numerical simulations obtained from ATLAS Silvaco software.

中文翻译:

基于势垒解析模型的4H-SiC JBS二极管沟道区设计

摘要 在本文中,我们提出了一种用于设计 4H 多型碳化硅结势垒肖特基、JBS、二极管的工具,这些器件因其低导通电阻和高阻断电压而成为有前途的器件。我们的工具根据几何和物理参数以及掺杂浓度计算沟道区域的宽度,以便器件显示出与肖特基势垒二极管类似的正向电特性。它们的工作原理是通过控制电子载流子通过势垒的流动来定义的,势垒位于被 p + 型区域包围的肖特基金属接触下方的 n 型区域中。事实上,如果 p + -n 结的电场在平衡条件下扩展到整个沟道区域,感应势垒的高度可能高于传统肖特基内置电位的高度,并且会影响器件的电气特性,例如增加导通电压。尽管 4H-SiC JBS 二极管首先是在硅技术中开发的,但由于 4H-SiC p-n 结的电场具有更宽的空间电荷区,对于与 Si JBS 相同的掺杂浓度值,4H-SiC JBS 二极管更容易制造器件,从而使通道几何结构的设计约束更加宽松。我们的分析模型可以计算作为器件几何和物理参数的函数的势垒高度,并且可以评估势垒高于肖特基内置电压的最大沟道宽度。
更新日期:2021-05-01
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