With the technology node scaling down into nanometer range, the effect of parasitic inductance and capacitance between the interconnect lines on predicting single event crosstalk (SEC) has to be considered. An analytical model is proposed to evaluate SEC in nanometer CMOS circuits based on the equation circuit of single event transient and RLC distributed model of interconnect. The transfer function of the arbitrary segment of interconnects is deduced by applying KCL and KVL laws in Laplace domain. The accurate expression of SEC voltage is achieved by the operation of matrix polynomial. For convenient calculation, a third-order exponential model is used to describe the SEC voltage approximately. The simulation results at the technology nodes of 22 nm, 32 nm, 45 nm, 65 nm, and 90 nm show that in comparison to previous work, the analytical model has a significantly improved accuracy with an average error of only 2.19%.

中文翻译：

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用于预测纳米 CMOS 电路单事件 (SE) 串扰的分析模型

随着技术节点缩小到纳米范围，必须考虑互连线之间的寄生电感和电容对预测单事件串扰 (SEC) 的影响。基于单事件瞬态方程电路和互连的RLC分布式模型，提出了一种用于评估纳米CMOS电路中SEC的分析模型。通过在拉普拉斯域中应用 KCL 和 KVL 定律，推导出任意互连段的传递函数。SEC电压的准确表达是通过矩阵多项式的运算来实现的。为方便计算，采用三阶指数模型近似描述SEC电压。在 22 nm、32 nm、45 nm、65 nm 和 90 nm 技术节点的仿真结果表明，与之前的工作相比，