Thin‐film polyimides were prepared by solvent‐less vapor deposition polymerization (VDP) from pyromellitic dianhydride and 4,4′‐oxydianiline at 200 °C for liner dielectric formation of vertical interconnects called through‐silicon vias (TSVs) used in three‐dimensionally stacked integrated circuit (3DICs). FTIR, synchrotron XPS, and TDS were employed for determining the imidization ratio, and in addition, the mechanical properties, coefficient of thermal expansion and Young's modulus, of the VDP polyimide were characterized on Si wafers. The VDP polyimide exhibited extremely high conformality, beyond 75%, toward high‐aspect‐ratio deep Si holes, compared with conventional SiO₂ prepared by plasma‐enhanced chemical vapor deposition. The adhesion between the VDP polyimide and Si wafer was enhanced by an Al‐chelate promotor. Remarkably, the VDP polyimide TSV liner dielectrics showed much less thermomechanical stresses applied to the Si surrounding the TSVs than the plasma‐chemical vapor deposition SiO₂. The small keep‐out zone is expected for scaling down highly reliable 3DICs for the upcoming real artificial intelligence society.

中文翻译：

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通过气相沉积聚合法形成贯穿硅通孔的薄膜聚酰亚胺的晶圆上热机械特性：与等离子增强化学气相沉积SiO2的比较

薄膜聚酰亚胺是通过在200°C下由均苯四甲酸二酐和4,4'-二苯胺通过无溶剂气相沉积聚合（VDP）制备的，用于垂直互连的内衬电介质形成，称为三维硅通孔（TSV），用于三维堆叠式集成电路（3DIC）。FTIR，同步加速器XPS和TDS用于确定酰亚胺化率，此外，还对VDP聚酰亚胺的机械性能，热膨胀系数和杨氏模量进行了表征。与传统的SiO ₂相比，VDP聚酰亚胺对高纵横比的深Si孔显示出极高的一致性，超过75％通过等离子增强化学气相沉积制备。Al-螯合物促进剂增强了VDP聚酰亚胺和Si晶片之间的附着力。值得注意的是，与等离子化学气相沉积SiO ₂相比，VDP聚酰亚胺TSV衬里电介质表现出的热机械应力要小得多。小型的保护区有望为即将到来的真正的人工智能协会缩减高度可靠的3DIC。