In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance. The proposed ADPLL utilizes a low power and high resolution 3-bit flash TDC with foreground calibration to suppress the issues of process, voltage and temperature (PVT) spreads and achieves low jitter and low power ADPLL. To obtain the fast locking, a proposed dynamic bang-bang PFD is used. The proposed ADPLL takes only 5 iterations to achieve the locking from unlocked state. Additionally, ADPLL employs a wide range and low phase noise voltage controlled oscillator (VCO) based on inverters to obtain a reduced jitter in ADPLL. The proposed ADPLL is designed in 180-nm SCL digital CMOS technology at 1.8 V supply. It consumes a total power of 5.94 mW at 1.8 V. From the post layout simulations, the achieved FoM and periodic jitter is −227.6 dB and 1.71 ps respectively at an output frequency of 1.6 GHz. The achieved phase noise of proposed ADPLL is −131.2 dBc/Hz at offset of 100 MHz.

在当前工作中，设计了一种全数字锁相环架构（ADPLL），它采用了爆炸式相位频率检测器（BB-PFD）和基于3位闪存的时间数字转换器（TDC），以增强抖动和锁定时间表现。拟议中的ADPLL利用具有前景校准功能的低功耗，高分辨率3位闪存TDC来抑制工艺，电压和温度（PVT）扩展问题，并实现了低抖动和低功耗ADPLL。为了获得快速锁定，使用了建议的动态Bang-bang PFD。所提出的ADPLL仅需5次迭代即可实现从解锁状态的锁定。此外，ADPLL采用基于反相器的宽范围和低相位噪声压控振荡器（VCO）来降低ADPLL的抖动。拟议中的ADPLL是在180nm SCL数字CMOS技术下设计的（1）。8 V电源。它在1.8 V时消耗的总功率为5.94 mW。通过布局后仿真，在1.6 GHz的输出频率下，实现的FoM和周期性抖动分别为-227.6 dB和1.71 ps。拟议的ADPLL在100 MHz的偏移量处实现的相位噪声为-131.2 dBc / Hz。