A novel approach to developing an FPGA-based chirp signal generator using high-level synthesis implementation is proposed. OpenCL, which is a framework used for high-level synthesis (HLS) methodologies, is employed instead of the Verilog/VHDL language to program FPGA. OpenCL has been used for FPGA programming, particularly in high-performance computing applications. Utilizing OpenCL for FPGA development reduces development time because of the high-level abstraction of the code. However, compared to Verilog/VHDL, standard OpenCL does not enable direct access to the FPGA's I/O. In this study, the FPGA needs to access the I/O pins to communicate with the DAC and generate the chirp signal. Thus, direct access to the FPGA I/O pin from the OpenCL environment is required. Therefore, a new OpenCL component is developed to enable the FPGA to communicate with the DAC, thus allowing data streaming to generate the chirp signal. This OpenCL component enables us to stream the data from the FPGA to generate the chirp signal. Here, we demonstrate that by using OpenCL implementation, the FPGA can generate an I/Q chirp signal efficiently. Moreover, the same OpenCL kernel can be employed to generate different bandwidths of the chirp signal without having to reprogram the FPGA. To demonstrate the capability of the system, we generated the I/Q chirp signal from 1 MHz to 5 MHz, 5 MHz to 10 MHz, 10 MHz to 15 MHz and 15 MHz to 20 MHz for a period of 10 µs.

提出了一种使用高级综合实现开发基于FPGA的线性调频信号发生器的新方法。OpenCL是用于高级综合（HLS）方法的框架，它代替了Verilog / VHDL语言来对FPGA进行编程。OpenCL已用于FPGA编程，尤其是在高性能计算应用程序中。由于代码的高级抽象，将OpenCL用于FPGA开发可减少开发时间。但是，与Verilog / VHDL相比，标准的OpenCL不能直接访问FPGA的I / O。在本研究中，FPGA需要访问I / O引脚以与DAC通信并产生线性调频信号。因此，需要从OpenCL环境直接访问FPGA I / O引脚。因此，开发了一个新的OpenCL组件，以使FPGA与DAC通信，从而允许数据流产生线性调频信号。这个OpenCL组件使我们能够从FPGA流式传输数据以生成线性调频信号。在这里，我们演示了通过使用OpenCL实现，FPGA可以有效地生成I / Q线性调频信号。此外，可以使用相同的OpenCL内核来生成线性调频信号的不同带宽，而无需重新编程FPGA。为了演示系统的功能，我们在1 µs的时间内生成了从1 MHz到5 MHz，5 MHz到10 MHz，10 MHz到15 MHz和15 MHz到20 MHz的I / Q线性调频信号。我们证明了通过使用OpenCL实现，FPGA可以有效地产生I / Q线性调频信号。而且，可以使用相同的OpenCL内核来生成线性调频信号的不同带宽，而无需重新编程FPGA。为了演示系统的功能，我们在1 µs的时间内生成了从1 MHz到5 MHz，5 MHz到10 MHz，10 MHz到15 MHz和15 MHz到20 MHz的I / Q线性调频信号。我们证明了通过使用OpenCL实现，FPGA可以有效地生成I / Q线性调频信号。而且，可以使用相同的OpenCL内核来生成线性调频信号的不同带宽，而无需重新编程FPGA。为了演示系统的功能，我们在1 µs的时间内生成了从1 MHz到5 MHz，5 MHz到10 MHz，10 MHz到15 MHz和15 MHz到20 MHz的I / Q线性调频信号。