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Extreme reduction of on-resistance in vertical GaN p–n diodes by low dislocation density and high carrier concentration GaN wafers fabricated using oxide vapor phase epitaxy method
Applied Physics Express ( IF 2.3 ) Pub Date : 2020-07-02 , DOI: 10.35848/1882-0786/aba018
Junichi Takino 1, 2 , Tomoaki Sumi 1 , Yoshio Okayama 1 , Akira Kitamoto 2 , Masayuki Imanishi 2 , Masashi Yoshimura 2 , Naomi Asai 3 , Hiroshi Ohta 3 , Tomoyoshi Mishima 3 , Yusuke Mori 2
Affiliation  

Low dislocation density and low-resistance GaN wafers are in high demand for improving the performance of vertical GaN power devices. Recently, GaN wafers with the dislocation density of 8.8 × 10 4 cm −2 and the resistivity of 7.8 × 10 −4 Ω cm, were fabricated using oxide vapor phase epitaxy (OVPE). In this study, GaN p–n diodes on GaN wafers prepared by the OVPE method were evaluated for verifying their suitability as vertical GaN power devices. An extremely low-differential specific on-resistance of 0.08 mΩ cm 2 and a high breakdown voltage of 1.8 kV were obtained from forward and reverse I – V measurements.

中文翻译:

低位错密度和高载流子浓度的GaN晶圆采用氧化物气相外延法制造,可极大地降低垂直GaN p–n二极管的导通电阻

低位错密度和低电阻的GaN晶片对提高垂直GaN功率器件的性能有很高的要求。近来,使用氧化物气相外延(OVPE)制造位错密度为8.8×10 4 cm -2且电阻率为7.8×10 -4Ωcm的GaN晶片。在这项研究中,对通过OVPE方法制备的GaN晶片上的GaN p–n二极管进行了评估,以验证其是否适合用作垂直GaN功率器件。通过正向和反向IV测量获得了极低的0.08mΩcm 2的比导通电阻和1.8 kV的高击穿电压。
更新日期:2020-07-03
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