In single-phase power and energy applications, sliding discrete Fourier transform (SDFT) filter based quadrature signal generation is a well-known tool for designing advanced phase-locked loops (PLLs), particularly for applications where high disturbance rejection ability is demanded. The SDFT-based PLL, nevertheless, has a limited ability in achieving fast response (a response time more than one cycle of the nominal frequency). To deal with this problem, a synchronous reference frame PLL based on half-cycle DFT (HCDFT) is proposed, enabling a fast and accurate synchronisation even in distorted grid. In this study, the fundamental voltage of the PLL input signal is obtained by a HCDFT filter. Then, phase, frequency and amplitude can be detected by the improved synchronous reference frame phase-locked loop (SRF-PLL). Besides, in order to solve the phase error when the frequency changes, a phase compensator is used. The HCDFT-based SRF-PLL method proposed in this study is compared, through experimental results, with a number of conventional methods, showing that the phase can be estimated under grid voltage disturbances accurately and quickly, which verifies the effectiveness and superiority of the proposed algorithm.

中文翻译：

---

基于半周期DFT的同步参考帧单相锁相环（PLL）算法

在单相功率和能量应用中，基于滑动离散傅立叶变换（SDFT）滤波器的正交信号生成是用于设计高级锁相环（PLL）的众所周知的工具，特别是在需要高抗干扰能力的应用中。但是，基于SDFT的PLL在实现快速响应方面的能力有限（响应时间超过标称频率的一个周期）。为了解决这个问题，提出了一种基于半周期DFT（HCDFT）的同步参考帧PLL，即使在失真的电网中也可以实现快速而准确的同步。在这项研究中，PLL输入信号的基波电压由HCDFT滤波器获得。然后，可以通过改进的同步参考帧锁相环（SRF-PLL）来检测相位，频率和幅度。除了，为了解决频率变化时的相位误差，使用了相位补偿器。通过实验结果，将本研究中提出的基于HCDFT的SRF-PLL方法与许多常规方法进行了比较，表明可以在电网电压扰动下准确，快速地估计相位，从而验证了所提出方法的有效性和优越性。算法。