Demanded by ever-evolving data processing algorithms, field-programmable gate arrays (FPGAs) have become essential components of modern computing systems, thanks to their reconfigurable and distributed computing capabilities. However, FPGAs are among the very few integrated chips that still require long development cycles and high human efforts, even for industrial vendors. In this article, we introduce OpenFPGA, an open-source framework that can automate and significantly accelerate the development cycle of customizable FPGA architectures. OpenFPGA allows users to customize their FPGA architectures down to circuit-level details using a high-level architecture description language and autogenerate associated Verilog netlists which can be used in a backend flow to generate production-ready layouts. A generic Verilog-to-Bitstream generator is also provided, allowing end-users to implement practical applications on any FPGAs that OpenFPGA can support. Using OpenFPGA, we demonstrate less than 24-h layout generation of two FPGA fabrics, which are based on a Stratix-like architecture built with a commercial 12-nm standard cell library and 40-nm custom cells, respectively.

中文翻译：

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OpenFPGA：用于敏捷原型可定制 FPGA 的开源框架

应不断发展的数据处理算法的需求，现场可编程门阵列 (FPGA) 凭借其可重构和分布式计算能力已成为现代计算系统的重要组成部分。然而，FPGA 是极少数仍然需要较长开发周期和大量人力的集成芯片之一，即使对于工业供应商也是如此。在本文中，我们将介绍 OpenFPGA，这是一个开源框架，可以自动化并显着加快可定制 FPGA 架构的开发周期。OpenFPGA 允许用户使用高级架构描述语言自定义他们的 FPGA 架构到电路级细节，并自动生成相关的 Verilog 网表，这些网表可用于后端流程以生成生产就绪布局。还提供了一个通用的 Verilog-to-Bitstream 生成器，允许最终用户在 OpenFPGA 支持的任何 FPGA 上实现实际应用。使用 OpenFPGA，我们展示了两种 FPGA 结构的布局生成时间不到 24 小时，它们基于类似 Stratix 的架构，分别使用商业 12-nm 标准单元库和 40-nm 定制单元构建。