Synthesis and simulation of hardware design can take hours before results are available even for small changes. In contrast, software development embraced live programming to boost productivity. This article proposes LiveHD, an open-source incremental framework for hardware synthesis and simulation that provides feedback within seconds. Three principles for incremental design automation are presented. LiveHD uses an unified VLSI data model, LGraph, to support the implementation of incremental principles for synthesis and simulation. LiveHD also employs a tree-like high-level intermediate representation to interface modern hardware description languages. We present early results comparing with commercial and open source tools. LiveHD can provides feedback for the synthesis, placement, and routing in < 30 s for most changes tested with negligible QoR impact. For the incremental simulation, LiveHD is capable of getting any simulation cycle in under 2 s for a 256 RISC-V core design.

中文翻译：

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LiveHD：高效的直播硬件开发流程


即使对于很小的变化，硬件设计的综合和仿真也可能需要几个小时才能获得结果。相比之下，软件开发采用实时编程来提高生产力。本文提出了 LiveHD，这是一种用于硬件合成和仿真的开源增量框架，可在几秒钟内提供反馈。提出了增量设计自动化的三个原则。 LiveHD使用统一的VLSI数据模型LGraph来支持综合和仿真增量原则的实施。 LiveHD 还采用树状高级中间表示来连接现代硬件描述语言。我们展示了与商业和开源工具进行比较的早期结果。 LiveHD 可以在 < 30 秒内为大多数经过测试的更改提供合成、布局和布线反馈，而对 QoR 的影响可以忽略不计。对于增量仿真，LiveHD 能够在 2 秒内获得 256 RISC-V 内核设计的任何仿真周期。