RTL simulation is a critical tool for hardware design but its current slow speed often bottlenecks the whole design process. Simulation speed becomes even more crucial for agile and open-source hardware design methodologies, because the designers not only want to iterate on designs quicker, but they may also have less resources with which to simulate them. In this article, we execute multiple simulators and analyze them with hardware performance counters. We find some open-source simulators not only outperform a leading commercial simulator, they also achieve comparable or higher instruction throughput on the host processor. Although advanced optimizations may increase the complexity of the simulator, they do not significantly hinder instruction throughput. Our findings make the case that there is significant room to accelerate software simulation and open-source simulators are a great starting point for researchers.

中文翻译：

---

一个加速软件 RTL 仿真的案例

RTL 仿真是硬件设计的关键工具，但其目前缓慢的速度往往会成为整个设计过程的瓶颈。对于敏捷和开源硬件设计方法而言，仿真速度变得更加重要，因为设计人员不仅希望更快地迭代设计，而且他们还可能拥有更少的资源来进行仿真。在本文中，我们执行多个模拟器并使用硬件性能计数器对其进行分析。我们发现一些开源模拟器不仅性能优于领先的商业模拟器，它们还在主机处理器上实现了相当或更高的指令吞吐量。尽管高级优化可能会增加模拟器的复杂性，但它们不会显着阻碍指令吞吐量。