Device-design optimization of a ferroelectric-gated vertical tunnel field-effect transistor (TFET) with a germanium source is performed using a technology computer-aided design simulation tool. In order to improve the device performance as well as to suppress the ambipolar current, the vertical length of the ferroelectric layer in the gate stack of the TFET is engineered. When the channel region is partially controlled with the ferroelectric layer, the device performance such as the on-state drive current and subthreshold swing (SS) can be improved (e.g. ##IMG## [http://ej.iop.org/images/0268-1242/35/8/085010/sstab8e63ieqn1.gif] {${I_{{\text{ON}}}}$} ∼ 3.08 × 10 –4 A/ μ m, ##IMG## [http://ej.iop.org/images/0268-1242/35/8/085010/sstab8e63ieqn2.gif] {${I_{{\text{ON}}}}/{I_{{\text{OFF}}}}$} ∼ 3.28 × 10 10 , and a minimum SS of 22 mV/decade at 300 K). Moreover, the ambipolar current ( ##IMG## {${I_{{\...}

中文翻译：

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铁电门控垂直隧道场效应晶体管抑制双极性电流的器件设计优化

使用计算机辅助设计仿真技术，可以对带有锗源的铁电门控垂直隧道场效应晶体管（TFET）进行设备设计优化。为了改善器件性能并抑制双极性电流，设计了TFET栅极堆叠中铁电层的垂直长度。当通过铁电层部分控制沟道区域时，可以改善器件性能，例如导通状态驱动电流和亚阈值摆幅（SS）（例如，## IMG ## [http://ej.iop.org/ images / 0268-1242 / 35/8/085010 / sstab8e63ieqn1.gif] {$ {I _ {{\ text {ON}}}} $}约3.08×10 –4 A /μm，## IMG ## [http ：//ej.iop.org/images/0268-1242/35/8/085010/sstab8e63ieqn2.gif] {$ {I _ {{\ text {ON}}}}} / {I _ {{\ text {OFF}} }} $}〜3.28×10 10，在300 K时最小SS为22 mV /十倍频。