In this paper, low‐cost and two‐cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area‐constrained structure, and in the second structure, a high‐speed implementation of the PRINCE cipher is presented. The substitution box (S‐box) and the inverse of S‐box (S‐box⁻¹) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low‐cost structure, the S‐boxes and S‐boxes⁻¹ are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two‐cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180‐nm CMOS technology and Virtex‐4 and Virtex‐6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works.

中文翻译：

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PRINCE轻量级分组密码的低成本和两周期硬件结构

本文介绍了PRINCE轻量级分组密码的低成本和两周期硬件结构。在第一种结构中，我们提出了一种区域受限结构，在第二种结构中，提出了PRINCE密码的高速实现。替换框（S-box）和逆框（S-box ^-1）块是PRINCE密码中最复杂的块。这些模块由具有低关键路径延迟的高效结构设计。在低成本结构中，S盒和S盒^-1在轮次计算和PRINCE密码的中间步骤之间共享。因此，所提出的体系结构是基于最少数量的计算资源实现的。PRINCE密码的两周期实现由处理元素（PE）设计，PE是一种通用且可重新配置的元素。这种结构具有规则形式，具有最小数量的控制信号。可以在180nm CMOS技术以及Virtex-4和Virtex-6 FPGA系列中实现拟议结构的实现结果。与其他人的相关工作相比，基于结果提出的结构具有更好的关键路径延迟和吞吐量。