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Study on interfacial trap location induced subthreshold slope degradation extracted by random telegraph noise for high-k/metal gate FinFET devices
Microelectronics Reliability ( IF 1.6 ) Pub Date : 2020-08-01 , DOI: 10.1016/j.microrel.2020.113728
Yi-Lin Yang , Wenqi Zhang , Yu-Lin Chen , Wen-Kuan Yeh

Abstract In this work, constant voltage stress (CVS) induced interfacial trap and its effect on subthreshold slope (SS) degradation were studied for the first time by the random telegraph noise (RTN) technique. Part of the generated traps were located in the interfacial layer (IL) under CVS. Both the trap location and trapping number show a large impact on SS degradation, and it could be demonstrated by RTN. If the trap depths are similar, more traps cause more severe SS degradation. If the trap depths are different, shallow trap shows larger impact on SS degradation than that of deep trap even if the trapping charges of deep trap are more than that of shallow trap.

中文翻译:

高k/金属栅极FinFET器件随机电报噪声提取的界面陷阱位置诱导亚阈值斜率退化研究

摘要 本文首次利用随机电报噪声(RTN)技术研究了恒压应力(CVS)诱导的界面陷阱及其对亚阈值斜率(SS)退化的影响。部分生成的陷阱位于 CVS 下的界面层 (IL) 中。陷阱位置和陷阱数量都对 SS 退化有很大影响,RTN 可以证明这一点。如果陷阱深度相似,更多的陷阱会导致更严重的 SS 退化。如果陷阱深度不同,即使深陷阱的俘获电荷比浅陷阱多,浅陷阱对SS降解的影响也比深陷阱大。
更新日期:2020-08-01
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