This work reports a compact behavioral model for gated-synaptic memory. The model is developed in Verilog-A for easy integration into computer-aided design of neuromorphic circuits using emerging memory. The model encompasses various forms of gated synapses within a single framework and is not restricted to only a single type. The behavioral theory of the model is described in detail along with a full list of the default parameter settings. The model includes parameters such as a device's ideal set time, threshold voltage, general evolution of the conductance with respect to time, decay of the device's state, etc. Finally, the model's validity is shown via extensive simulation and fitting to experimentally reported data on published gated-synapses.

中文翻译：

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神经形态电路的紧凑门控突触模型

这项工作报告了门控突触记忆的紧凑行为模型。该模型是在 Verilog-A 中开发的，可轻松集成到使用新兴内存的神经形态电路的计算机辅助设计中。该模型在单个框架内包含各种形式的门控突触，并不仅限于单一类型。详细描述了模型的行为理论以及默认参数设置的完整列表。该模型包括诸如设备的理想设置时间、阈值电压、电导随时间的一般演变、设备状态的衰减等参数。 最后，通过广泛的模拟和拟合实验报告的数据显示了模型的有效性已发布门控突触。