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An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray
Integration ( IF 1.9 ) Pub Date : 2020-07-01 , DOI: 10.1016/j.vlsi.2020.06.005
Junyan Qian , Bisheng Huang , Hao Ding , Zhide Zhou , Lingzhong Zhao , Zhongyi Zhai

Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs, capacitance and dynamic energy dissipation. An existing work proved that the high performance VLSI subarray can be constructed in polynomial time using network flow algorithm. However, because of the disadvantage of the previous network model and the low-performing of standard network flow algorithms for reconfiguration, the efficiency of these algorithms is poor for constructing the high performance VLSI subarray. In this paper, we present an efficient multiple shortest augmenting paths algorithm for rapidly constructing high performance VLSI array. Firstly, we proposed an efficient data structure to construct the network model of the VLSI array with faults, which can dramatically reduce the size of the model compared with previous algorithm. Secondly, a multiple shortest augmenting path algorithm based on the new data structure is proposed, which can significant reduce the running time. Finally, we conduct solid experiments to highlight the efficiency of the proposed method in terms of the running time compared to the standard network flow algorithms. The experimental results show that on a 64 × 64 host array with 0.1% faults, the size of the network model can be reduced by about 50% and the average improvements in running time is up to 85.10% compared with four standard network flow algorithms.



中文翻译:

一种构建高性能VLSI子阵列的高效多重最短扩充路径算法

重新配置有故障的VLSI阵列的高性能子阵列是使用最少的长互连构造一个最大的目标阵列,这可以减少通信成本,电容和动态能耗。现有工作证明,可以使用网络流算法在多项式时间内构造高性能VLSI子阵列。然而,由于先前的网络模型的缺点以及用于重新配置的标准网络流算法的性能低下,这些算法的效率对于构造高性能VLSI子阵列是很差的。在本文中,我们提出了一种用于快速构建高性能VLSI阵列的有效的多个最短扩充路径算法。首先,我们提出了一种有效的数据结构来构建有故障的VLSI阵列的网络模型,与以前的算法相比,它可以大大减小模型的大小。其次,提出了一种基于新数据结构的多重最短扩充路径算法,可以大大减少运行时间。最后,我们进行了可靠的实验,与标准网络流算法相比,在运行时间方面突出了所提出方法的效率。实验结果表明,与四种标准网络流算法相比,在故障率为0.1%的64×64主机阵列上,网络模型的大小可以减少约50%,运行时间的平均改善率高达85.10%。提出了一种基于新数据结构的多重最短增广路径算法,可以大大减少运行时间。最后,我们进行了可靠的实验,与标准网络流算法相比,在运行时间方面突出了所提出方法的效率。实验结果表明,与四种标准网络流算法相比,在故障率为0.1%的64×64主机阵列上,网络模型的大小可以减少约50%,运行时间的平均改善率高达85.10%。提出了一种基于新数据结构的多重最短增广路径算法,可以大大减少运行时间。最后,我们进行了可靠的实验,与标准网络流算法相比,在运行时间方面突出了所提出方法的效率。实验结果表明,与四种标准网络流算法相比,在故障率为0.1%的64×64主机阵列上,网络模型的大小可以减少约50%,运行时间的平均改善率高达85.10%。

更新日期:2020-07-01
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