This article presents a 32-GHz frequency-modulated continuous wave (FMCW) modulator based on the phase-locked loop (PLL) with nested sub-PLL structure in a 65-nm CMOS process. With the sub-PLL, the low-pass effect in phase domain is realized, reducing the noise folding effect, quantization noise, and spurs due to the delta sigma modulator (DSM). To achieve good stability and phase noise performance, both the phase-domain model and the phase noise model are analyzed and simulated. Based on these models, the chirp linearity is discussed and simulated, which helps to determine the design parameters and verifies the linearity improvement. The measurement results illustrate that in fractional- $N$ mode, the nested-PLL achieves the phase noise of −91 dBc/Hz at 1-MHz offset frequency and the fractional spurs of less than −54 dBc at 30.78-GHz output frequency. In FMCW mode, the proposed modulator achieves a triangular chirp with 1.08–2.16-GHz bandwidth at about 32-GHz center frequency. In addition, the measured root mean square (rms) frequency errors of 400 and 770 kHz are achieved with the ramp slopes of 1.08 GHz/93 $\mu \text{s}$ and 2.16 GHz/93 $\mu \text{s}$ , respectively. Measurement results prove the improvements of the phase noise and chirp linearity with the sub-PLL. Including all pads, the chip occupies a silicon area of 1.5 mm², and consumes 62-mW dc power.

中文翻译：

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采用 65-nm CMOS 工艺、具有 2.16-GHz 带宽的 32-GHz 基于嵌套 PLL 的 FMCW 调制器

本文介绍了一种 32 GHz 调频连续波 (FMCW) 调制器，该调制器基于锁相环 (PLL)，采用 65 纳米 CMOS 工艺，具有嵌套 sub-PLL 结构。使用 sub-PLL，实现了相位域中的低通效应，减少了噪声折叠效应、量化噪声和由 delta sigma 调制器 (DSM) 引起的杂散。为了获得良好的稳定性和相位噪声性能，对相域模型和相位噪声模型进行了分析和仿真。基于这些模型，讨论和模拟chirp线性度，这有助于确定设计参数并验证线性度改进。测量结果表明，在分数- $N$ 模式下，嵌套 PLL 在 1-MHz 偏移频率下实现 -91 dBc/Hz 的相位噪声，在 30.78-GHz 输出频率下实现小于 -54 dBc 的分数杂散。在 FMCW 模式下，建议的调制器在大约 32 GHz 中心频率下实现了 1.08-2.16 GHz 带宽的三角啁啾。此外，400 和 770 kHz 的测量均方根 (rms) 频率误差是通过 1.08 GHz/93 的斜坡斜率实现的 $\mu \text{s}$ 和 2.16 GHz/93 $\mu \text{s}$ ， 分别。测量结果证明使用 sub-PLL 可以改善相位噪声和线性调频。包括所有焊盘在内，该芯片占用的硅面积为 1.5 mm ²，并消耗 62-mW 直流功率。