In this paper, we present a compact design for the code based signature called LEDAsig with side channel resistance. Existing implementations concentrate on the high-speed feature while few of them have considerations on area or power efficiency which are particularly decisive for low-cost or power constrained IoT applications. We propose an area-efficient FPGA architecture for systematically rotating the QC-LDGM codes amongst the block RAMs with read-first mode. Additionally, the side channel vulnerability of LEDAsig is carefully examined, and protective masking schemes are introduced accordingly to safeguard our design from power analysis attacks. Effectiveness of these schemes is verified on SAKURA-G FPGA board. Up till now, the design presented in this work is the most compact one and also the first side-channel secure one addressing first-order and (univariate) second-order differential power analysis for the code based signature schemes in the open literature. We show for instance that our first-order (second-order) protected implementation can sign a signature in 117 (203) ms on a Xilinx Spartan-6 FPGA, occupying only 622 (1142) slices, and therefore is a prospective candidate for post-quantum signature schemes in low-resource settings.

中文翻译：

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具有侧信道弹性的可重构设备的基于代码的紧凑签名

在本文中，我们提出了一种基于代码的签名的紧凑设计，称为 LEDAsig，具有侧通道电阻。现有的实施专注于高速特性，而很少考虑面积或功率效率，这对于低成本或功率受限的物联网应用尤为重要。我们提出了一种面积高效的 FPGA 架构，用于在具有读取优先模式的块 RAM 之间系统地旋转 QC-LDGM 代码。此外，仔细检查了 LEDAsig 的侧信道漏洞，并相应地引入了保护屏蔽方案，以保护我们的设计免受功耗分析攻击。这些方案的有效性在 SAKURA-G FPGA 板上得到了验证。至目前为止，这项工作中提出的设计是最紧凑的设计，也是第一个侧信道安全设计，用于解决公开文献中基于代码的签名方案的一阶和（单变量）二阶差分功率分析。例如，我们展示了我们的一阶（二阶）保护实现可以在 117 (203) ms 内在 Xilinx Spartan-6 FPGA 上签署签名，仅占用 622 (1142) 个切片，因此是发布的潜在候选者- 低资源环境中的量子签名方案。