Carbon nanotube field effect transistor (CN-MOSFET) is attractive for the realization of future monolithic three-dimensional (M3D) memory circuits with ultra-high integration density, capacity, efficiency, and speed. However, the yield of each vertically-stacked active layer can be significantly degraded by the presence of metallic carbon nanotubes (m-CNs) caused by process imperfections. The potential integration density benefits of M3D circuits also may not be fully realized by the large area skews between different layers within standard cells. In this paper, ultra-high density and robust M3D static random-access memory (SRAM) cells are proposed for tolerance to the removal of m-CNs. By minimizing the skew and area of each device layer, the 16Kibit memory arrays with the proposed SRAM cells enhance the integration density by up to 82.92% as compared to the carbon-based traditional 2D and previously published M3D memory arrays. While achieving high functional yield and maintaining robust read/write operations, the proposed SRAM circuits enhance the overall electrical quality by up to 27.41x as compared to the alternative 2D and M3D memory arrays.

中文翻译：

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用于提高产量和集成密度的单片 3D 碳纳米管存储器

碳纳米管场效应晶体管（CN-MOSFET）对于实现具有超高集成密度、容量、效率和速度的未来单片三维（M3D）存储电路具有吸引力。然而，由于工艺缺陷导致金属碳纳米管 (m-CN) 的存在，每个垂直堆叠的活性层的产量都会显着降低。M3D 电路的潜在集成密度优势也可能无法通过标准单元内不同层之间的大面积偏差来完全实现。在本文中，提出了超高密度和稳健的 M3D 静态随机存取存储器 (SRAM) 单元，以耐受 m-CN 的去除。通过最小化每个器件层的偏斜和面积，带有建议的 SRAM 单元的 16Kibit 存储器阵列将集成密度提高了 82。与基于碳的传统 2D 和之前发布的 M3D 存储阵列相比，提高了 92%。在实现高功能产量和保持稳健的读/写操作的同时，与替代的 2D 和 M3D 存储器阵列相比，所提出的 SRAM 电路将整体电气质量提高了 27.41 倍。