This article analyses and demonstrates a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions. The proposed gear-shift algorithm scales up the PLL bandwidth for faster acquisition and orderly reduces it for jitter performance. The PLL contains a digitally controlled oscillator (DCO) based on transformer feedback with a tunable source-bridged capacitor, which allows for a low phase noise (PN) over a wide tuning range (FoM of −184 dBc/Hz and FoM $_{T}$ of −191 dBc/Hz) and for a fine frequency resolution. The PLL occupies 0.09-mm² core area and exhibits 220 fs rms jitter while consuming 25 mW, giving FoM_RMS of −239 dB. Its frequency acquisition time improves from 780 to 45 $\mu \text{s}$ with the gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channels’ frequencies of IEEE-802.11ad, allows a transmitter (TX) error vector magnitude (EVM) down to −35.9 dB assuming a TX signal to the noise-plus-distortion ratio (SNDR) of 40 dB, and, thus, is capable of supporting 256 quadrature amplitude modulation (QAM).

中文翻译：

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分析用于毫米波通信的具有 220-fs RMS 抖动的 28-nm CMOS 快速锁定 Bang-Bang 数字 PLL

本文分析并演示了用于毫米波 (mm-wave) 通信的 22.5–27.7-GHz 快速锁定低相位噪声 bang-bang 数字锁相环 (PLL)。离散时间 PLL 模型与理论传递函数一起，可以深入了解自动带宽控制的功能、换档算法对快速锁定的影响以及不同的噪声贡献。所提出的换档算法扩大了 PLL 带宽以加快采集速度，并有序地减少它以提高抖动性能。PLL 包含一个基于变压器反馈的数控振荡器 (DCO)，带有一个可调源桥接电容器，可在宽调谐范围（-184 dBc/Hz 的 FoM 和 FoM）内实现低相位噪声 (PN) $_{T}$ −191 dBc/Hz) 和精细的频率分辨率。PLL 占用 0.09-mm ²核心面积并表现出 220 fs rms 抖动，同时消耗 25 mW，提供−239 dB 的FoM _RMS。其频率采集时间从 780 提高到 45 $\mu \text{s}$ 与换档算法。对于 60 GHz 通信，倍频因子为 2.5，该 PLL 涵盖 IEEE-802.11ad 的所有六个通道频率，允许发射器 (TX) 误差矢量幅度 (EVM) 低至 −35.9 dB，假设 TX 信号为40 dB 的噪声加失真比 (SNDR)，因此能够支持 256 正交幅度调制 (QAM)。