Closed-loop neuromodulation for the treatment of neurological disorders requires monitoring of the brain activity uninterruptedly even during neurostimulation. This article presents a bidirectional 32-channel CMOS neural interface that can record neural activity during stimulation. Each channel consists of a dc-coupled $\Delta ^{2} \Sigma $ -modulated analog-to-digital converter (neural-ADC), which records slow potentials (< 0.1 Hz) while accommodating rail-to-rail dc offset using a spectrum-shaping front-end. This front-end equalizes the neural signal spectrum before signal quantization, which reduces the energy consumption and silicon area. Upon detection of a large artifact by an in-channel event-triggered digital block, the modulator feedback DAC tracks the artifact with step sizes incrementing in a radix-2 exponential form, preventing the neural-ADC from saturation. Upon tracking the artifact, the multi-bit DAC step size is reduced to zoom into the input neural signal at the highest recording resolution. The modulator’s multi-bit DAC is reused in a time-shared fashion as a current-mode stimulator with no area overhead. The $\Delta ^{2} \Sigma $ -ADC consumes 1.7 $\mu \text{W}$ from 0.6-V/1.2-V digital/analog supplies and time-shares the modulator’s feedback DAC as the multi-bit current-mode stimulator operating at 3.3 V. The ADC occupies a silicon area of 0.023 mm² in the 130-nm CMOS and achieves a signal-to-noise-and-distortion ratio (SNDR) of 70 dB over the 500-Hz bandwidth and an equivalent noise efficiency factor (NEF) of 2.86 without a stand-alone front-end amplifier. The 32-channel bidirectionally interfacing prototype is validated in the in vivo whole brain of a rodent.

中文翻译：

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具有盲刺激伪影抑制的跟踪和缩放神经模数转换器

用于治疗神经系统疾病的闭环神经调节需要不间断地监测大脑活动，即使在神经刺激期间也是如此。本文介绍了一种双向 32 通道 CMOS 神经接口，可以记录刺激过程中的神经活动。每个通道由一个直流耦合 $\Delta ^{2} \Sigma $ - 调制模数转换器（神经 ADC），它记录慢电位（< 0.1 Hz），同时使用频谱整形前端适应轨到轨直流偏移。该前端在信号量化之前均衡了神经信号频谱，从而减少了能耗和硅面积。在通道内事件触发数字模块检测到大伪影后，调制器反馈 DAC 以基数 2 指数形式递增的步长跟踪伪影，防止神经 ADC 饱和。跟踪伪像后，多位 DAC 步长会减小，以最高记录分辨率放大输入神经信号。调制器的多位 DAC 以分时方式重新用作电流模式激励器，没有面积开销。这 $\Delta ^{2} \Sigma $ -ADC消耗1.7 $\mu \text{W}$ 由 0.6-V/1.2-V 数字/模拟电源和时间共享调制器的反馈 DAC 作为在 3.3V 下运行的多位电流模式刺激器。ADC在 130-nm CMOS 中占据 0.023 mm ²的硅面积并且在没有独立前端放大器的情况下，在 500 Hz 带宽内实现了 70 dB 的信噪比 (SNDR) 和 2.86 的等效噪声效率因数 (NEF)。32 通道双向接口原型在体内 啮齿动物的全脑。