Effect of the Gate Volume on the Performance of Printed Nanosheet Network-Based Transistors,ACS Applied Electronic Materials

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Effect of the Gate Volume on the Performance of Printed Nanosheet Network-Based Transistors
ACS Applied Electronic Materials ( IF 4.3 ) Pub Date : 2020-06-30 , DOI: 10.1021/acsaelm.0c00368
Domhnall O’Suilleabhain ₁ , Adam G. Kelly ₁ , Ruiyuan Tian ₁ , Cian Gabbett ₁ , Dominik Horvath ₁ , Jonathan N. Coleman ₁

Affiliation

Demonstration of high-performance, all-printed transistors fabricated only from networks of two-dimensional nanosheets would represent a significant advance in printed electronics. However, such devices have only been shown to work via electrolytic gating. Under those circumstances, both channel/electrolyte and gate/electrolyte interfaces show significant capacitances which, when unoptimized, lead to reduced device performance. Here, we fabricate a range of printed thin-film transistors (TFTs) with WSe₂ and graphene nanosheet networks acting as the channel and gate electrodes. We find that transistor operation depends sensitively on the ratio of the gate electrode to channel volume such that effective mobility is only maximized when the gate volume is >10 times larger than the channel volume. These results indicate that all-printed, all-nanosheet stacked heterostructure TFTs will require relatively thick gates to operate effectively.

中文翻译：

栅极体积对基于印刷纳米片网络晶体管的性能的影响

仅由二维纳米片网络制成的高性能，全印刷晶体管的演示将代表印刷电子领域的重大进步。但是，这种设备仅显示为通过电解浇口工作。在这种情况下，通道/电解质界面和栅极/电解质界面均显示出显着的电容，如果未对其进行优化，则会导致器件性能下降。在这里，我们用WSe ₂制造了一系列印刷薄膜晶体管（TFT）。石墨烯纳米片网络充当沟道和栅电极。我们发现晶体管的操作敏感地取决于栅电极与沟道体积的比率，从而仅当栅体积大于沟道体积的10倍时，有效迁移率才会最大化。这些结果表明，全印刷，全纳米片堆叠的异质结构TFT将需要相对较厚的栅极才能有效地工作。

更新日期：2020-07-28

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