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A Tight I/O Lower Bound for Matrix Multiplication
ACM Transactions on Mathematical Software ( IF 2.7 ) Pub Date : 2020-07-07 , DOI: 10.1145/3362694
Tyler M Smith 1 , Robert A van de Geijn 1
Affiliation  

A tight lower bound for required I/O when computing a matrix-matrix multiplication on a processor with two layers of memory is established. Prior work obtained weaker lower bounds by reasoning about the number of phases needed to perform C:=AB, where each phase is a series of operations involving S reads and writes to and from fast memory, and S is the size of fast memory. A lower bound on the number of phases was then determined by obtaining an upper bound on the number of scalar multiplications performed per phase. This paper follows the same high level approach, but improves the lower bound by considering C:=AB+C instead of C:=AB, and obtains the maximum number of scalar fused multiply-adds (FMAs) per phase instead of scalar additions. Key to obtaining the new result is the decoupling of the per-phase I/O from the size of fast memory. The new lower bound is 2mnk/ S - 2S where S is the size of fast memory. The constant for the leading term is an improvement of a factor 4/ 2. A theoretical algorithm that attains the lower bound is given, and how the state-of-the-art Goto's algorithm also in some sense meets the lower bound is discussed.

中文翻译:

矩阵乘法的严格 I/O 下限

当在具有两层存储器的处理器上计算矩阵-矩阵乘法时,建立了所需 I/O 的严格下限。先前的工作通过推理执行 C:=AB 所需的阶段数获得了较弱的下界,其中每个阶段是一系列操作,涉及 S 对快速内存的读取和写入,S 是快速内存的大小。然后通过获得每个阶段执行的标量乘法数的上限来确定阶段数的下限。本文遵循相同的高级方法,但通过考虑 C:=AB+C 而不是 C:=AB 来改进下界,并获得每相而不是标量加法的最大标量融合乘法加法 (FMA) 数量。获得新结果的关键是将每阶段 I/O 与快速存储器的大小分离。新的下限是 2mnk/S - 2S,其中 S 是快速内存的大小。前项的常数是因子 4/ 2 的改进。给出了达到下限的理论算法,并讨论了最先进的 Goto 算法在某种意义上如何满足下限。
更新日期:2020-07-07
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