Recent trends in deep convolutional neural networks (DCNNs) impose hardware accelerators as a viable solution for computer vision and speech recognition. The Orlando SoC architecture from STMicroelectronics targets exactly this class of problems by integrating hardware-accelerated convolutional blocks together with DSPs and on-chip memory resources to enable energy-efficient designs of DCNNs. The main advantage of the Orlando platform is to have runtime configurable convolutional accelerators that can adapt to different DCNN workloads. This opens new challenges for mapping the computation to the accelerators and for managing the on-chip resources efficiently. In this work, we propose a runtime design space exploration and mapping methodology for runtime resource management in terms of on-chip memory, convolutional accelerators, and external bandwidth. Experimental results are reported in terms of power/performance scalability, Pareto analysis, mapping adaptivity, and accelerator utilization for the Orlando architecture mapping the VGG-16, Tiny-Yolo(v2), and MobileNet topologies.

中文翻译：

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超低功耗 Orlando SoC 的 DCNN 的运行时设计空间探索和映射

深度卷积神经网络 (DCNN) 的最新趋势将硬件加速器作为计算机视觉和语音识别的可行解决方案。STMicroelectronics 的 Orlando SoC 架构正是针对此类问题，将硬件加速卷积块与 DSP 和片上存储器资源集成在一起，以实现 DCNN 的节能设计。Orlando 平台的主要优势是具有运行时可配置的卷积加速器，可以适应不同的 DCNN 工作负载。这为将计算映射到加速器和有效管理片上资源带来了新的挑战。在这项工作中，我们提出了一种运行时设计空间探索和映射方法，用于运行时资源管理，包括片上存储器、卷积加速器、和外部带宽。在功率/性能可扩展性、帕累托分析、映射适应性和加速器利用率方面报告了实验结果，用于映射 VGG-16、Tiny-Yolo(v2) 和 MobileNet 拓扑的 Orlando 架构。