This work introduces Single Instruction Multi-Thread Express (SIMT-X), a general-purpose Central Processing Unit (CPU) microarchitecture that enables Graphics Processing Units (GPUs)-style SIMT execution across multiple threads of the same program for high throughput, while retaining the latency benefits of out-of-order execution, and the programming convenience of homogeneous multi-thread processors. SIMT-X leverages the existing Single Instruction Multiple Data (SIMD) back-end to provide CPU/GPU-like processing on a single core with minimal overhead. We demonstrate that although SIMT-X invokes a restricted form of Out-of-Order (OoO), the microarchitecture successfully captures a majority of the benefits of aggressive OoO execution using at most two concurrent register mappings per architectural register, while addressing issues of partial dependencies and supporting a general-purpose Instruction Set Architecture (ISA).

中文翻译：

---

SIMT-X

这项工作引入了单指令多线程 Express (SIMT-X)，这是一种通用的中央处理单元 (CPU) 微架构，它可以跨同一程序的多个线程执行图形处理单元 (GPU) 式 SIMT，以实现高吞吐量，同时保留了乱序执行的延迟优势，以及同构多线程处理器的编程便利性。SIMT-X 利用现有的单指令多数据 (SIMD) 后端以最小的开销在单核上提供类似 CPU/GPU 的处理。我们证明，尽管 SIMT-X 调用了一种受限形式的乱序 (OoO)，但该微架构成功地利用了每个架构寄存器最多两个并发寄存器映射，成功地获得了激进的 OoO 执行的大部分好处，