Traditional memory technologies face severe challenges in meeting the ever-increasing power and memory bandwidth requirements for high-performance computing and big-data analyses. Several emerging memory technologies are promising as the replacements of SRAM or DRAM. Among them, STT-MRAM can be used to replace SRAM as the last-level cache (LLC). However, it suffers from high write energy and latency. In this article, we investigate data patterns written from SRAM-based upper-level cache to STT-MRAM-based LLC to explore the write energy reduction potential. Depending on the data layout within a cache line, redundant bits can be identified and eliminated from write back operations to save STT-MRAM write energy. We also propose a dynamic profiling method to accommodate different application characteristics. The extensive simulation results show that write energy can be saved by 37.05% ∼ 38.89% for static profiling and 19.76% ∼ 34.29% for dynamic profiling.

中文翻译：

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具有数据模式表征的基于 STT-MRAM 的末级高速缓存的回写能量优化

传统内存技术在满足高性能计算和大数据分析不断增长的功率和内存带宽要求方面面临严峻挑战。几种新兴的存储技术有望替代 SRAM 或 DRAM。其中，STT-MRAM可以用来代替SRAM作为最后一级缓存（LLC）。然而，它受到高写入能量和延迟的影响。在本文中，我们研究了从基于 SRAM 的上层缓存写入基于 STT-MRAM 的 LLC 的数据模式，以探索降低写入能量的潜力。根据高速缓存行内的数据布局，可以识别冗余位并将其从回写操作中消除，以节省 STT-MRAM 写入能量。我们还提出了一种动态分析方法来适应不同的应用程序特征。